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EM78P142
8-Bit Microprocessor with OTP ROM
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
January 2008
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2008 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) P.O. Box 601 Cupertino, CA 95015 USA Tel: +1 408 366-8225 Fax: +1 408 366-8225
Shanghai: Elan Microelectronics Shanghai, Ltd. #23, Zone 115, Lane 572, Bibo Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 4 5 6 General Description ................................................................................................ 1 Features ................................................................................................................... 1 Pin Assignment ....................................................................................................... 2 Pin Description........................................................................................................ 3 4.1 EM78P142SS10 ............................................................................................... 3 Block Diagram ......................................................................................................... 4 Function Description .............................................................................................. 5 6.1 Operational Registers ....................................................................................... 5
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 R0 (Indirect Address Register) .......................................................................... 5 R1 (Time Clock).................................................................................................. 5 R2 (Program Counter) and Stack ....................................................................... 5 6.1.3.1 Data Memory Configuration................................................................. 7 R3 (Status Register) ........................................................................................... 8 R4 (RAM Select Register) .................................................................................. 8 R5 ~ R6 (Port 5 ~ Port 6).................................................................................... 8 R7 (Port 7) .......................................................................................................... 9 R8 (AISR: ADC Input Select Register) ............................................................. 10 R9 (ADCON: ADC Control Register) ................................................................ 12 RA (ADOC: ADC Offset Calibration Register) .................................................. 13 RB (ADDATA: Converted Value of ADC) .......................................................... 13 RC (ADDATA1H: Converted Value of ADC) ..................................................... 13 RD (ADDATA1L: Converted Value of ADC) ...................................................... 14 RE (Interrupt Status 2 and Wake-up Control Register) .................................... 14 RF (Interrupt Status 2 Register)........................................................................ 15 R10 ~ R3F ........................................................................................................ 15 A (Accumulator) ................................................................................................ 16 CONT (Control Register) .................................................................................. 16 IOC50 ~ IOC70 (I/O Port Control Register)...................................................... 16 IOC80 (TCCA Control Register) ....................................................................... 17 IOC90 (TCCB and TCCC Control Register) ..................................................... 17 IOCA0 (IR and TCCC Scale Control Register)................................................. 18 IOCB0 (Pull-down Control Register)................................................................. 19 IOCC0 (Open-drain Control Register) .............................................................. 19 IOCD0 (Pull-high Control Register) .................................................................. 19 IOCE0 (WDT Control Register and Interrupt Mask Register 2)........................ 20 IOCF0 (Interrupt Mask Register) ...................................................................... 21 IOC51 (TCCA Timer) ........................................................................................ 21 IOC61 (TCCB Timer) ........................................................................................ 22 IOC71 (TCCBH/MSB Timer)............................................................................. 22
6.2
Special Purpose Registers.............................................................................. 16
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 6.2.13 6.2.14
Product Specification (V1.0) 01.25.2008
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Contents
6.2.15 6.2.16 6.2.17 6.2.18 6.2.19 6.2.20 6.2.21 6.2.22
IOC81 (TCCC Timer) ........................................................................................ 22 IOC91 (Low-Time Register).............................................................................. 23 IOCA1 (High Time Register)............................................................................. 23 IOCB1 High/Low Time Scale Control Register)................................................ 23 IOCC1 (TCC Prescaler Timer).......................................................................... 24 IOCD1 (LVD Control Register) ......................................................................... 25 IOCE1 (Output Sink Select Control Register) .................................................. 26 IOCF1 (Pull-high Control Register)................................................................... 27
6.3 6.4 6.5
TCC/WDT and Prescaler ................................................................................ 27 I/O Ports ......................................................................................................... 28
6.4.1 6.5.1 Usage of Port 5 Input Change Wake-up/Interrupt Function ............................. 30 Reset and Wake-up Operation ......................................................................... 31 6.5.1.1 Wake-up and Interrupt Modes Operation Summary.......................... 33 6.5.1.2 Register Initial Values after Reset ..................................................... 38 6.5.1.3 Controller Reset Block Diagram ........................................................ 43 The T and P Status under Status Register ....................................................... 43
Reset and Wake-up ........................................................................................ 31
6.5.2
6.6 6.7
Interrupt .......................................................................................................... 44 Analog-To-Digital Converter (ADC) ................................................................. 46
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)............................... 46 6.7.1.1 R8 (AISR: ADC Input Select Register) .............................................. 46 6.7.1.2 R9 (ADCON: ADC Control Register) ................................................. 47 6.7.1.3 RA (ADOC: AD Offset Calibration Register) ...................................... 48 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) ............. 49 ADC Sampling Time ......................................................................................... 49 AD Conversion Time......................................................................................... 49 ADC Operation during Sleep Mode .................................................................. 49 Programming Process/Considerations ............................................................. 50 6.7.6.1 Programming Process ....................................................................... 50 6.7.6.2 Sample Demo Programs ................................................................... 51 Overview........................................................................................................... 53 Function Description ......................................................................................... 54 Programming the Related Registers ................................................................ 56 Overview........................................................................................................... 57 Function Description ......................................................................................... 57 Programming the Related Registers ................................................................ 59 Oscillator Modes ............................................................................................... 60 Crystal Oscillator/Ceramic Resonators (Crystal) .............................................. 61 External RC Oscillator Mode ............................................................................ 64 Internal RC Oscillator Mode ............................................................................. 65
Product Specification (V1.0) 01.25.2008
6.7.2 6.7.3 6.7.4 6.7.5 6.7.6
6.8
Infrared Remote Control Application/PWM Waveform Generation .................. 53
6.8.1 6.8.2 6.8.3
6.9
Timer .............................................................................................................. 57
6.9.1 6.9.2 6.9.3 6.10.1 6.10.2 6.10.3 6.10.4
6.10 Oscillator ........................................................................................................ 60
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Contents
6.11 Power-on Considerations................................................................................ 66
6.11.1 Programmable WDT Time-out Period .............................................................. 66 6.11.2 External Power-on Reset Circuit ...................................................................... 66 6.11.3 Residual Voltage Protection ............................................................................. 67
6.12 Code Option ................................................................................................... 68
6.12.1 Code Option Register (Word 0) ........................................................................ 68 6.12.2 Code Option Register (Word 1) ........................................................................ 70 6.12.3 Customer ID Register (Word 2) ........................................................................ 71
6.13 Low Voltage Detector/Low Voltage Reset ....................................................... 72
6.13.1 Low Voltage Reset............................................................................................ 72 6.13.2 Low Voltage Detector........................................................................................ 72 6.13.2.1 IOCD1 (LVD Control Register) .......................................................... 72 6.13.2.2 RE (Interrupt Status 2 & Wake-up Control Register) ......................... 73 6.13.3 Programming Process ...................................................................................... 74
7 8
6.14 Instruction Set................................................................................................. 75 Absolute Maximum Ratings.................................................................................. 77 DC Electrical Characteristics................................................................................ 77 8.1 AD Converter Characteristic ........................................................................... 79 8.2 Device Characteristics .................................................................................... 80 AC Electrical Characteristic.................................................................................. 81 Timing Diagrams ................................................................................................... 82
9 10
APPENDIX
A B C D E Package Type ........................................................................................................ 83 Packaging Configuration ...................................................................................... 84 B.1 EM78P142SS10 ............................................................................................. 84 Quality Assurance and Reliability ........................................................................ 85 C.1 Address Trap Detect ....................................................................................... 85 How to Use the ICE 341N ...................................................................................... 86 Comparison between V-Package and U-Package Version.................................. 89 EM78P142-V Package ............................................................................................ 89 EM78P142-U Package............................................................................................ 89
Product Specification (V1.0) 01.25.2008
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Contents
Specification Revision History
Doc. Version 1.0 Revision Description Initial released version Date 2008/01/25
Item Level Voltage Reset Crystal mode Operating frequency range at 0C~ 70C IRC mode wake-up time ( Sleep Normal ) Condition: 5V, 4MHz Code Option 10s
EM78P142 4.0V, 3.5V, 2.4V DC ~ 16MHz, 4.5V DC ~ 8MHz, 3.0V DC ~ 4MHz, 2.1V
Added a Code Option NRM
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Product Specification (V1.0) 01.25.2008
EM78P142
8-Bit Microprocessor with OTP ROM
1
General Description
The EM78P142 is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. The series have an on-chip 2Kx13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user's OTP memory code. Three Code option bits are also available to meet user's requirements. With enhanced OTP-ROM features, the EM78P142 provide a convenient way of developing and verifying user's programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.
2
Features
CPU configuration
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2Kx13 bits on-chip ROM 80x8 bits on-chip registers (SRAM) 8-level stacks for subroutine nesting 4 programmable Level Voltage Detector (LVD) : 4.5V, 4.0V, 3.3V, 2.2V 3 programmable Level Voltage Reset (LVR) : 4.0V, 3.5V, 2.4V Less than 1.5 mA at 5V/4MHz Typically 15 A, at 3V/32kHz Typically 2 A, during sleep mode 3 bidirectional I/O ports: P5, P6, P7 8 I/O pins Wake-up port : P5 5 programmable pull-down I/O pins 6 programmable pull-high I/O pins 1 programmable open-drain I/O pins 2.1V~5.5V at 0C~70C (commercial) 2.3V~5.5V at -40C~85C (industrial) Crystal mode: DC ~ 16MHz, 4.5V; DC ~ 8MHz, 3V; DC ~ 4MHz, 2.1V ERC mode: DC ~ 16MHz, 4.5V; DC ~ 125ns inst. cycle, 4.5V DC ~ 8MHz, 3V; DC ~ 250ns inst. cycle, 3V IRC mode Oscillation mode: 16MHz, 4MHz, 1MHz, 455kHz
Drift Rate
Fast set-up time requires only 0.8ms (VDD: 5V Crystal: 4MHz, C1/C2: 30pF) in HXT2 mode and 10s in IRC mode (VDD: 5V, IRC: 4 MHz) Peripheral configuration
* * * *
Easily implemented IR (infrared remote control) 8-bit real time clock (TCC) with overflow interrupt 8-bit real time clock (TCCA, TCCC) and 16-bit real time clock (TCCB) with overflow interrupt 7-bit multi-channel Analog-to-Digital Converter with 12-bit resolution in Vref mode TCC, TCCA, TCCB, TCCC overflow interrupt Input-port status changed interrupt (wake up from sleep mode) ADC completion interrupt IR/PWM period match completion Low voltage detect (LVD) interrupt Programmable free running Watchdog Timer (4.5 ms : 18 ms) Power saving Sleep mode Selectable Oscillation mode Power-on voltage detector available (1.7V 0.1V) High EFT immunity (better performance at 4 MHz or below) 10 pin SSOP 150mil : EM78P142SS10J/S
I/O port configuration
* * * * * *
Five available interrupts
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Operating voltage range:
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Special Features:
* * * * *
Operating frequency range (base on 2 clocks):
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Package Type:
*
*
Note: Green products do not contain hazardous .substances.
Internal RC Frequency
Temperature (-40C~85C)
Voltage Process Total (2.3V~5.5V)
4 MHz 16 MHz 1 MHz 455kHz
5% 5% 5% 5%
5% 5% 5% 5%
4% 4% 4% 4%
14% 14% 14% 14%
All the four main frequencies can be trimmed by programming with four calibrated bits in the ICE341N Simulator. OTP is auto trimmed by ELAN Writer.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
*1
EM78P142
8-Bit Microprocessor with OTP ROM
3
Pin Assignment
Figure 3-1 EM78P142SS10
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Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
4
Pin Description
4.1 EM78P142SS10
Symbol Pin No. Type Function 5-bit General purpose input/output pins Pull-high/Pull-down Function Wake up from Sleep/Idle mode when the pin status changes Default value at power-on reset 1-bit General purpose input/output pin Pull-high/Open-drain Function Default value at power-on reset 2-bit General purpose input/output pins Default value at power-on reset When P71 is used as output function, it is an open drain pin 7-bit channel Analog-to-Digital Converter with 12-bit resolution. Defined by ADCON (R9)<1:0> If it remains at logic low, the device will be reset Wake-up from Sleep/Idle mode when pin status changes Voltage on /RESET must not exceed Vdd during normal mode Crystal type: Crystal input terminal. RC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator. RC type: Clock output with a duration of one instruction cycle time. External clock signal input. Power supply Ground
P50~P53 P55
1~3, 9~10
I/O
P67
6
I/O
P70~P71
8, 4
I/O
ADC0~ADC6
1~3, 6 8~10
I
/RESET
4
I
OSCI
9
I
OSCO
8
O
VDD VSS
7 5
- -
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
*3
EM78P142
8-Bit Microprocessor with OTP ROM
5
Block Diagram
Figure 5 EM78P142 Block Diagram
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Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6
Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock)
Incremented by the instruction cycle clock. Writable and readable as any other registers. The TCC prescaler counter (IOCC1) is assigned to TCC The contents of the IOCC1 register is cleared whenever -
* * *
a value is written to the TCC register. a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register) there is power-on reset, /RESET, or WDT time out reset.
6.1.3 R2 (Program Counter) and Stack
R3
Reset Vector Hardware Interrupt Vector 000H 003H
A10
A9 A8
A7 CALL RET RETL RETI
~
A0
~
021H
User Memory Space
0 PAGE0 0000~03FF 1 PAGE1 0400~07FF
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 Stack Level 8
On-chip Program Memory
7FFH
Figure 6-1 Program Counter Organization
R2 and hardware stacks are 11-bit wide. The structure is depicted in the table under Section 6.1.3.1 Data Memory Configuration. The configuration structure generates 2Kx13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. The contents of R2 are all set to "0"s when a reset condition occurs.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
*5
EM78P142
8-Bit Microprocessor with OTP ROM
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "LJMP" instruction allows direct loading of the program counter bits (A0~A10). Therefore, "LJMP" allows PC to jump to any location within 2K (211). "LCALL" instruction loads the program counter bits (A0 ~A10), and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within 2K (211) "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. Any instruction (except "ADD R2,A") that is written to R2 (e.g., "MOV R2, A", "BC R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2) except "LCALL" and "LJMP" instructions. The "LCALL" and "LJMP" instructions need two instructions cycle.
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Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.1.3.1
Address
Data Memory Configuration
R Page Registers IOCX0 Page Registers IOCX1 Page Registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
R0 (Indirect Addressing Register) R1 (Timer Clock) R2 (Program Counter) R3 (Status Register) R4 (RAM Select Register) R5 (Port 5) R6 (Port 6) R7 (Port 7) R8 (ADC Input Select Register R9 (ADC Control Register) RA (ADC Offset Calibration Register) (Converted value RB AD11~AD4 of ADC) RC (Converted value AD11~AD8 of ADC) (Converted value RD AD7~AD0 of ADC) RE (Interrupt Status 2 and Wake-up Control Register RF (Interrupt Status Register 1)
Reserve Reserve Reserve Reserve Reserve IOC50 (I/O Port Control Register) IOC60 (I/O Port Control Register) IOC70 (I/O Port Control Register) IOC80 (TCCA Control Register) IOC90 (TCCB and TCCC Control Register) (IR and TCCC Scale IOCA0 Control Register) IOCB0 (Pull-down Control Register) IOCC0 (Open-drain Control Register)
Reserve Reserve Reserve Reserve Reserve IOC51 (TCCA Timer) IOC61 (TCCB LSB Timer) IOC71 (TCCB HSB Timer) IOC81 (TCCC Timer) IOC91 (Low-Time Register) IOCA1 (High-Time Register) IOCB1 (High-Time and Low-Time Scale Control Register)
IOCC1 (TCC Prescaler Control)
IOCD0 (Pull-high Control Register) IOCD1 (LVD Control Register) IOCE0 (WDT Control Register and Interrupt Mask Register 2) IOCF0 (Interrupt Mask Register 1) IOCE1 (High Output Sink Current) IOCF1 (Pull-high Control Register)
General Registers 1F 20 3F
Bank 0
Bank 1
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
*7
EM78P142
8-Bit Microprocessor with OTP ROM
6.1.4 R3 (Status Register)
Bit 7 RST Bit 6 IOCS Bit 5 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 7 (RST): Bit of reset type Set to "1" if wake-up from sleep on pin change, comparator status change, or AD conversion completed. Set to "0" if wake-up from other reset types. Bit 6 (IOCS): Select the Segment of IO control register 0 = Segment 0 (IOC50 ~ IOCF0) selected 1 = Segment 1 (IOC51 ~ IOCC1) selected Bit 5: Bit 4 (T): Not used (reserved) Time-out bit. Set to "1" by the "SLEP" and "WDTC" commands or during power on, and reset to "0" by WDT time-out (for more details see Section 6.5.2, The T and P Status under Status Register). Bit 3 (P): Power-down bit. Set to "1" during power-on or by a "WDTC" command and reset to "0" by a "SLEP" command (see Section 6.5.2, The T and P Status under Status Register for more details). Bit 2 (Z): Bit 1 (DC): Bit 0 (C): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Auxiliary carry flag Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7: Bit 6: Bits 5~0: Set to "0" all the time Used to select Bank 0 or Bank 1 of the register Used to select a register (Address: 00~0F, 10~3F) in indirect addressing mode. See table under Section 6.1.3.1 Data Memory Configuration.
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 & R6 are I/O registers.
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Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.1.7 R7 (Port 7)
Bit EM78P142 ICE341N
Note: R7 is an I/O register.
7 `0' C3
6 `0' C2
5 `0' C1
4 `0' C0
3 `0' RCM1
2 `0' RCM0
1 I/O I/O
0 I/O I/O
Bit 7 ~ Bit 2: [With EM78P142]: Unimplemented, read as `0'. mode. In IRC oscillator mode of ICE341N simulator, these are the IRC mode selection bits and IRC calibration bits. Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Frequency (MHz) (1-36%) x F (1-31.5%) x F (1-27%) x F (1-22.5%) x F (1-18%) x F (1-13.5%) x F (1-9%) x F (1-4.5%) x F F (default) (1+4.5%) x F (1+9%) x F (1+135%) x F (1+18%) x F (1+22.5%) x F (1+27%) x F (1+31.5%) x F
[With Simulator (C3~C0, RCM1, and RCM0)]: IRC calibration bits in IRC oscillator
Note: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode. Hence, they are shown for reference only. Definite values depend on the actual process.
2. Similar way of calculation is also applicable for low frequency mode.
Bit 3 and Bit 2 (RCM1, RCM0): IRC mode selection bits
RCM 1 1 1 0 0 RCM 0 1 0 1 0 Frequency (MHz) 4 (default) 16 1 455kHz
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
*9
EM78P142
8-Bit Microprocessor with OTP ROM
6.1.8 R8 (AISR: ADC Input Select Register)
The AISR register individually defines the I/O Port as analog input or as digital I/O.
Bit 7 `0' Bit 6 ADE6 Bit 5 ADE5 Bit 4 ADE4 Bit 3 ADE3 Bit 2 ADE2 Bit 1 ADE1 Bit 0 ADE0
Bit 7:
This bit must be set to "0" all the time.
Bit 6 (ADE6): AD converter enable bit of P55 pin 0 = Disable ADC6, P55 functions as I/O pin 1 = Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P70 pin 0 = Disable ADC5, P70 functions as I/O pin 1 = Enable ADC5 to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P67 pin 0 = Disable ADC4, P67 functions as I/O pin 1 = Enable ADC4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P53 pin 0 = Disable ADC3, P53 functions as I/O pin 1 = Enable ADC3 to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P52 pin 0 = Disable ADC2, P52 functions as I/O pin 1 = Enable ADC2 to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 functions as I/O pin 1 = Enable ADC1 to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P50 pin 0 = Disable ADC0, P50 functions as I/O pin 1 = Enable ADC0 to function as analog input pin
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Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
NOTE The P55/OSCI/ADC6 pin cannot be applied to OSCI and ADC6 at the same time. If P55/OSCI/ADC6 functions as OSCI oscillator input pin, then ADE6 bit for R8 must be "0" and ADIS2~0 do not select " 110". The P55/OSCI/ADC6 pin priority is as follows: P55/OSCI/ADC6 Pin Priority High OSCI Medium ADC6 Low P55
The P70/OSCO/ADC5 pin cannot be applied to OSCO and ADC5 at the same time. If P70/OSCO/ADC5 acts as OSCO oscillator input pin, then ADE5 bit for R8 must be "0" and ADIS2~0 do not select "101". The P70/OSCO/ADC5 pin priority is as follows: P70/OSCO/ADC5 Pin Priority High OSCO Medium ADC5 Low P70
The P67/IR OUT/ADC4 pin cannot be applied to IR OUT and ADC4 at the same time. If P67/IR OUT/ADC4 functions as ADC4 analog input pin, then IROUTE bit for IOCA0 must be "0".. If P67/IR OUT/ADC4 functions as IR OUT analog input pin, then ADE4 bit for R8 must be "0" and ADIS2~0 do not select "100". The P67/IR OUT/ADC4 pin priority is as follows: P67/IR OUT/ADC4 Pin Priority High ADC4 Medium IR OUT Low P67
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
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EM78P142
8-Bit Microprocessor with OTP ROM
6.1.9 R9 (ADCON: ADC Control Register)
Bit 7 "0" Bit 6 CKR1 Bit 5 CKR0 Bit 4 ADRUN Bit 3 ADPD Bit 2 ADIS2 Bit 1 ADIS1 Bit 0 ADIS0
Bit 7:
This bit must be set to "0" all the time
Bit 6 and Bit 5 (CKR1 and CKR0): The prescaler of the ADC oscillator clock rate 00 = 1: 16 (default value) 01 = 1: 4 10 = 1: 64 11 = 1: 8
CPUS 1 1 1 1 0 CKR1:CKR0 00 01 10 11 xx Operation Mode Fosc/16 Fosc/4 Fosc/64 Fosc/8 Internal RC Max. Operation Frequency 4 MHz 1 MHz 16 MHz 2 MHz -
Bit 4 (ADRUN): ADC starts to RUN. 1 = an AD conversion is started. This bit can be set by software 0 = Reset upon completion of the conversion. This bit cannot be reset through software Bit 3 (ADPD): ADC Power-down mode 1 = ADC is operating 0 = Switch off the resistor reference to save power even while the CPU is operating. Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select 000 = ADIN0/P50 001 = ADIN1/P51 010 = ADIN2/P52 011 = ADIN3/P53 100 = ADIN4/P67 101 = ADIN5/P70 110 = ADIN6/P55 111 = not used These bits can only be changed when the ADIF bit and the ADRUN bit are both low. See Section 6.1.14, RE (Interrupt Status 2 and Wake-up Control Register).
12 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.1.10 RA (ADOC: ADC Offset Calibration Register)
Bit 7 CALI Bit 6 SIGN Bit 5 VOF[2] Bit 4 VOF[1] Bit 3 VOF[0] Bit 2 "0" Bit 1 "0" Bit 0 "0"
Bit 7 (CALI):
Calibration enable bit for ADC offset 0 = disable Calibration 1 = enable Calibration
Bit 6 (SIGN):
Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2] 0 0 0 0 1 1 1 1 VOF[1] 0 0 1 1 0 0 1 1 VOF[0] 0 1 0 1 0 1 0 1
EM78P142
ICE341 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
Bit 2 ~ Bit 0:
Unimplemented, read as `0'
6.1.11 RB (ADDATA: Converted Value of ADC)
Bit 7 AD11 Bit 6 AD10 Bit 5 AD9 Bit 4 AD8 Bit 3 AD7 Bit 2 AD6 Bit 1 AD5 Bit 0 AD4
When the AD conversion is completed, the result is loaded into the ADDATA. The ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2 and Wake-up Control Register). RB is read only.
6.1.12 RC (ADDATA1H: Converted Value of ADC)
Bit 7 "0" Bit 6 "0" Bit 5 "0" Bit 4 "0" Bit 3 AD11 Bit 2 AD10 Bit 1 AD9 Bit 0 AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2 and Wake-up Control Register). RC is read only.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 13
EM78P142
8-Bit Microprocessor with OTP ROM
6.1.13 RD (ADDATA1L: Converted Value of ADC)
Bit 7 AD7 Bit 6 AD6 Bit 5 AD5 Bit 4 AD4 Bit 3 AD3 Bit 2 AD2 Bit 1 AD1 Bit 0 AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared and the ADIF is set. See Section 6.1.14, RE (Interrupt Status 2 and Wake-up Control Register). RD is read only
6.1.14 RE (Interrupt Status 2 and Wake-up Control Register)
Bit 7 /LVD Bit 6 LVDIF Bit 5 ADIF Bit 4 "0" Bit 3 ADWE Bit 2 "0" Bit 1 ICWE Bit 0 LVDWE
Note: 1. RE <6, 5> can be cleared by instruction but cannot be set.
2. IOCE0 is the interrupt mask register. 3. Reading RE will result to "logic AND" of the RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0 = low voltage is detected 1 = low voltage is not detected or LVD function is disabled
Bit 6 (LVDIF):
Low Voltage Detector interrupt flag LVDIF is reset to "0" by software.
Bit 5 (ADIF):
Interrupt flag for analog to digital conversion. Set when AD conversion is completed. Reset by software. 0 = no interrupt occurs 1 = interrupt request
Bit 4: Bit 3 (ADWE):
This bit must be set to "0" all the time. ADC wake-up enable bit 0 = Disable ADC wake-up 1 = Enable ADC wake-up When AD Conversion enters sleep/idle mode, this bit must be set to "Enable".
Bit 2: Bit 1 (ICWE):
This bit must be set to "0" all the time. Port 5 input change to wake-up status enable bit 0 = Disable Port 5 input change to wake-up status 1 = Enable Port 5 input change to wake-up status When Port 5 change enters sleep/idle mode, this bit must be set to "Enable".
14 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit 0 = Disable Low Voltage Detect wake-up 1 = Enable Low Voltage Detect wake-up When the Low Voltage Detect is used to enter an interrupt vector or to wake-up the IC from sleep/idle with Low Voltage Detect running, the LVDWE bit must be set to "Enable".
6.1.15 RF (Interrupt Status 2 Register)
Bit 7 LPWTIF Bit 6 HPWTIF Bit 5 TCCCIF Bit 4 TCCBIF Bit 3 TCCAIF Bit 2 "0" Bit 1 ICIF Bit 0 TCIF
Note: 1. "1" means there is interrupt request, "0"
2. RF can be cleared by instruction but cannot be set. 3. IOCF0 is the interrupt mask register. 4. Reading RF will result to "logic AND" of the RF and IOCF0
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software. Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software. Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by software. Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCB overflows. Reset by software. Bit 3 (TCCAIF): Bit 2: Bit 1 (ICIF): Bit 0 (TCIF): TCCA overflow interrupt flag. Set when TCCA overflows. Reset by software. This bit must be set to "0" all the time. Port 5 input status change interrupt flag. Set when Port 5 input changes. Reset by software. TCC overflow interrupt flag. Set when TCC overflows. Reset by software.
6.1.16 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 15
EM78P142
8-Bit Microprocessor with OTP ROM
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7 "0" Bit 6 INT Bit 5 "0" Bit 4 "0" Bit 3 PSTE Bit 2 PST2 Bit 1 PST1 Bit 0 PST0
Note: The CONT register is both readable and writable. Bit 6 is read only.
Bit 7: Bit 6 (INT):
This bit must be set to "0" all the time. Interrupt enable flag 0 = masked by DISI or hardware interrupt 1 = enabled by the ENI/RETI instructions This bit is readable only.
Bit 5 ~ Bit 4 : Bit 3 (PSTE):
These bits must set to "0" all the time. Prescaler enable bit for TCC 0 = prescaler disable bit. TCC rate is 1:1. 1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2 0 0 0 0 1 1 1 1 PST1 0 0 1 1 0 0 1 1 PST0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Note: Tcc time-out period [1/Fosc x prescaler x (256 - Tcc cnt) x 1
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
"0" defines the relative I/O pin as output "1" sets the relative I/O pin into high impedance IOC50 <7, 6, 4>, IOC60 <6~0> : These bits must set to "0" all the time, Other bits could be readable and writable. IOC70 registers are all readable and writable
16 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.4 IOC80 (TCCA Control Register)
Bit 7 - Bit 6 - Bit 5 - Bit 4 "0" Bit 3 "0" Bit 2 TCCAEN Bit 1 "0" Bit 0 "0"
Note: Bit 2 of the IOC80 register is both readable and writable.
Bits 7 ~ 5: Bits 4 ~ 3: Bit 2 (TCCAEN):
Not used These bits must set to "0" all the time. TCCA enable bit 0 = disable TCCA 1 = enable TCCA These bits must set to "0" all the time.
Bits 1 ~ 0:
6.2.5 IOC90 (TCCB and TCCC Control Register)
Bit 7 TCCBHE Bit 6 TCCBEN Bit 5 "0" Bit 4 "0" Bit 3 - Bit 2 TCCCEN Bit 1 "0" Bit 0 "0"
Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of the timer 1 = Enable the most significant byte of TCCBH TCCB is a 16-bit timer. 0 = Disable the most significant byte of TCCBH (default value) TCCB is an 8-bit timer. Bit 6 (TCCBEN): TCCB enable bit 0 = disable TCCB 1 = enable TCCB Bits 5 ~ 4: Bit 3: These bits must set to "0" all the time. Not used.
Bit 2 (TCCCEN): TCCC enable bit 0 = disable TCCC 1 = enable TCCC Bits 1 ~ 0: These bits must set to "0" all the time.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 17
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
Bit 7 TCCCSE Bit 6 TCCCS2 Bit 5 TCCCS1 Bit 4 TCCCS0 Bit 3 IRE Bit 2 HF Bit 1 LGP Bit 0 IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC An 8-bit timer is provided as scale for TCCC and IR-Mode. When in IR-Mode, TCCC timer scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Figure 6-11 in Section 6.8.2, Function Description). 0 = scale disable bit, TCCC rate is 1:1 1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4 Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to determine the scale ratio of TCCC as shown below:
TCCCS2 0 0 0 0 1 1 1 1 TCCCS1 0 0 1 1 0 0 1 1 TCCCS0 0 1 0 1 0 1 0 1 TCCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (IRE):
Infrared Remote Enable bit 0 = Disable IRE, i.e., disable H/W Modulator Function. The IROUT pin is fixed at a high level and the TCCC is an Up Timer. 1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67 is defined as IROUT. If HF=1, the TCCC timer scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation (see Figure 6-11 in Section 6.8.2, Function Description). When HF=0, the TCCC is an Up Timer
Bit 2 (HF):
High Frequency bit 0 = PWM application. IROUT waveform is achieved base on the high-pulse width timer and low-pulse width timer which determine the high time width and low time width respectively. 1 = IR application mode. The low-time segments of the pulse generated by the Fcarrier frequency modulation (see Figure 6-11 in Section 6.8.2, Function Description)
18 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Bit 1 (LGP):
Long Pulse. 0 = The high-time and low-time registers are valid 1 = The high-time register is ignored. A single pulse is generated.
Bit 0 (IROUTE): Control bit used to define the P67 (IROUT) pin function 0 = P67 defined as bi-directional I/O pin 1 = P67 defined as IROUT. Under this condition, the I/O control bit of P67 (Bit 7 of IOC60) must be set to "0"
6.2.7 IOCB0 (Pull-down Control Register)
Bit 7 "1" Bit 6 "1" Bit 5 /PD55 Bit 4 "1" Bit 3 /PD53 Bit 2 /PD52 Bit 1 /PD51 Bit 0 /PD50
The IOCB0 register is both readable and writable. Bits 7 ~ 6 and Bit 4: These bits must set to "1" all the time. Bit 5 (/PD55): Control bit is used to enable the pull-down function of the P55 pin 0 = Enable internal pull-down 1 = Disable internal pull-down Bit 3 (/PD53): Control bit is used to enable the pull-down function of the P53 pin Bit 2 (/PD52): Control bit is used to enable the pull-down function of the P52 pin Bit 1 (/PD51): Control bit is used to enable the pull-down function of the P51 pin Bit 0 (/PD50): Control bit is used to enable the pull-down function of the P50 pin.
6.2.8 IOCC0 (Open-drain Control Register)
Bit 7 /OD67 Bit 6 "1" Bit 5 "1" Bit 4 "1" Bit 3 "1" Bit 2 "1" Bit 1 "1" Bit 0 "1"
The IOCC0 register is both readable and writable. Bit 7 (/OD67): Control bit is used to enable the open-drain output of the P67 pin 0 = Enable open-drain output 1 = Disable open-drain output Bits 6 ~ 0: These bits must set to "1" all the time
6.2.9 IOCD0 (Pull-high Control Register)
Bit 7 "1" Bit 6 "1" Bit 5 /PH55 Bit 4 "1" Bit 3 /PH53 Bit 2 /PH52 Bit 1 /PH51 Bit 0 /PH50
The IOCD0 register is both readable and writable.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 19
EM78P142
8-Bit Microprocessor with OTP ROM
Bits 7 ~ 6 and Bit 4: These bits must set to "1" all the time. Bit 5 (/PH55): Control bit is used to enable the pull-high function of the P55 pin 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 3 (/PH53): Control bit is used to enable the pull-high function of the P53 pin. Bit 2 (/PH52): Control bit is used to enable the pull-high function of the P52 pin. Bit 1 (/PH51): Control bit is used to enable the pull-high function of the P51 pin. Bit 0 (/PH50): Control bit is used to enable the pull-high function of the P50 pin.
6.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2)
Bit 7 WDTE Bit 6 "0" Bit 5 ADIE Bit 4 "0" Bit 3 PSWE Bit 2 PSW2 Bit 1 PSW1 Bit 0 PSW0
Bit 7 (WDTE): Control bit used to enable Watchdog Timer 0 = Disable WDT 1 = Enable WDT WDTE is both readable and writable. Bit 6: Bit 5 (ADIE): This bit must be set to "0" all the time. ADIF interrupt enable bit 0 = disable ADIF interrupt 1 = enable ADIF interrupt Bit 4: This bit must be set to "0" all the time.
Bit 3 (PSWE): Prescaler enable bit for WDT 0 = prescaler disable bit, WDT rate is 1:1 1 = prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2 0 0 0 0 1 1 1 1 PSW1 0 0 1 1 0 0 1 1 PSW0 0 1 0 1 0 1 0 1 WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
20 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.11 IOCF0 (Interrupt Mask Register)
Bit 7 LPWTIE Bit 6 HPWTIE Bit 5 TCCCIE Bit 4 TCCBIE Bit 3 TCCAIE Bit 2 "0" Bit 1 ICIE Bit 0 TCIE
Note: The IOCF0 register is both readable and writable.
Individual interrupt is enabled by setting to "1" its associated control bit in the IOCF0 and in IOCEO Bits 4 and 5. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 6-7 Interrupt Input Circuit under Section 6 Interrupt.
Bit 7 (LPWTIE): LPWTIF interrupt enable bit 0 = Disable LPWTIF interrupt 1 = Enable LPWTIF interrupt Bit 6 (HPWTIE): HPWTIF interrupt enable bit 0 = Disable HPWTIF interrupt 1 = Enable HPWTIF interrupt Bit 5 (TCCCIE): TCCCIF interrupt enable bit 0 = Disable TCCCIF interrupt 1 = Enable TCCCIF interrupt Bit 4 (TCCBIE): TCCBIF interrupt enable bit 0 = Disable TCCBIF interrupt 1 = Enable TCCBIF interrupt Bit 3 (TCCAIE): TCCAIF interrupt enable bit 0 = Disable TCCAIF interrupt 1 = Enable TCCAIF interrupt Bit 2: Bit 1 (ICIE): This bit must be set to "0" all the time. ICIF interrupt enable bit 0 = Disable ICIF interrupt 1 = Enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit. 0 = Disable TCIF interrupt 1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Timer)
The IOC51 (TCCA) is an 8-bit clock timer. It is also an Up Timer and it can be read, written to, and cleared on any reset condition.
TCCA Timeout period =
FOSC x 256 - TCCA cnt x 1
(
1
)
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 21
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.13 IOC61 (TCCB Timer)
The IOC61 (TCCB) is an 8-bit clock timer for the least significant byte of TCCBX (TCCB). It is also an Up Timer, and it can be read, written to, and cleared on any reset condition.
6.2.14 IOC71 (TCCBH/MSB Timer)
The IOC71 (TCCBH/MSB) is an 8-bit clock Timer for the most significant byte of TCCBX (TCCBH). It can be read, written to, and cleared on any reset condition. When TCCBHE (IOC90) is "0," then TCCBH is disabled. When TCCBHE is"1," then TCCB is a 16-bit timer. When TCCBH is disabled:
TCCB Timeout period =
When TCCBH is enabled:
FOSC x 256 - TCCB cnt x 1
(
1
)
TCCB Timeout period =
FOSC x
[ 65536
- TCCBH x 256 + TCCB cnt x 1
(
1
)
]
6.2.15 IOC81 (TCCC Timer)
IOC81 (TCCC) is an 8-bit clock timer that can be extended to 16-bit timer. It can be read, written to and cleared on any reset condition. If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC timer scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation (see Figure 6-11 in Section 6.8.2, Function Description). Then the TCCC value will be TCCC predicted value. When HF = 0 or IRE = 0, the TCCC is an Up Timer. In TCCC Up Timer mode:
TCCC Timeout period =
1
FOSC x Scaler (IOCA0 ) x 256 - TCCC cnt x 1
(
)
When HF = 1 and IRE = 1, TCCC timer scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation. In IR mode:
Fcarrier = 2
{ [ 1 + Decimal TCCC Value (IOC81) ] x TCCC Scale (IOCA0)}
where
FT
FT =
FOSC 1
Product Specification (V1.0) 01.25.2008
22 *
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.16 IOC91 (Low-Time Register)
The 8-bit Low-time register controls the active or Low segment of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as follows:
Low Time Width =
{ [ 1 + Decimal Low Time Value (IOC91)] x Low Time Scale (IOCB1) }
FT
where
FT =
FOSC 1
When an interrupt is generated by the Low time down counter underflow (when enabled), the next instruction will be fetched from Address 015H (Low time).
6.2.17 IOCA1 (High Time Register)
The 8-bit High-time register controls the inactive or High period of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated as follows:
High Time Width =
{ [ 1 + Decimal High Time Value (IOCA1)] x High Time Scale (IOCB1) }
FT
where
FT =
FOSC 1
When an interrupt is generated by the High time down counter underflow (when enabled), the next instruction will be fetched from Address 012H (High time).
6.2.18 IOCB1 High/Low Time Scale Control Register)
Bit 7 HTSE Bit 6 HTS2 Bit 5 HTS1 Bit 4 HTS0 Bit 3 LTSE Bit 2 LTS2 Bit 1 LTS1 Bit 0 LTS0
Bit 7 (HTSE): High-time scale enable bit 0 = scale disable bit, High-time rate is 1:1 1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 23
EM78P142
8-Bit Microprocessor with OTP ROM Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:
HTS2 0 0 0 0 1 1 1 1 HTS1 0 0 1 1 0 0 1 1 HTS0 0 1 0 1 0 1 0 1 High-time Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (LTSE): Low-time scale enable bit. 0 = scale disable bit, Low-time rate is 1:1 1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0. Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:
LTS2 0 0 0 0 1 1 1 1 LTS1 0 0 1 1 0 0 1 1 LTS0 0 1 0 1 0 1 0 1 Low-time Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
6.2.19 IOCC1 (TCC Prescaler Timer)
TCC prescaler timer can be read and written to:
PST2 PST1 PST0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Bit 7 V Bit 6 V V Bit 5 V V V Bit 4 V V V V Bit 3 V V V V V Bit 2 V V V V V V Bit 1 V V V V V V V Bit 0 V V V V V V V V TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
V = valid value
The TCC prescaler timer is assigned to TCC (R1). The contents of the IOCC1 register are cleared when one of the following occurs: a value is written to the TCC register a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of CONT) power-on reset, /RESET WDT time out reset
24 * Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.20 IOCD1 (LVD Control Register)
Bit EM78P142 ICE341N 7 TYPE1 6 TYPE0 5 LVR1 4 LVR0 3 2 1 LVD1 LVD1 0 LVD0 LVD0 LVDIE LVDEN LVDIE LVDEN
Bits 7~6 (Type 1 ~ Type 0): Type selection for EM78P142.
Type 1, Type 0 11 10 01 00 MCU Type No use No use EM78P142 - 10Pin No use
Bits 5~4 (LVR1 ~ LVR0): Low Voltage Reset enable bits.
LVR1, LVR0 11 10 01 00 VDD Reset Level 2.4V 3.5V 4.0V VDD Release Level 2.6V 3.7V 4.2V NA (Power-on Reset)
Note: The IOCD1 <3> register is both readable and writable.
Individual interrupt is enabled by setting to "1" its associated control bit in the IOCD1 <4>. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 6-8 Interrupt Input Circuit under Section 6.6 Interrupt.
Bit 3 (LVDIE): Low voltage Detector interrupt enable bit. 0 = Disable Low voltage Detector interrupt. 1 = Enable Low voltage Detector interrupt. When a Low Voltage Detect is used to enter an interrupt vector or enter next instruction, the LVDIE bit must be set to "Enable". Bit 2 (LVDEN): Low Voltage Detector enable bit 0 = Low voltage detector disable 1 = Low voltage detector enable Bits 1~0 (LVD1:0): Low Voltage Detector level bits.
LVDEN 1 1 1 1 0 LVD1, LVD0 11 10 01 00 xx LVD Voltage Interrupt Level Vdd 2.2V Vdd > 2.2V Vdd 3.3V Vdd > 3.3V Vdd 4.0V Vdd > 4.0V Vdd 4.5V Vdd > 4.5V NA /LVD 0 1 0 1 0 1 0 1 0
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 25
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.21 IOCE1 (Output Sink Select Control Register)
Bit EM78P142 ICE341N 7 6 5 4 IDLE IDLE 3 "0" "0" 2 "0" "0" 1 "0" "0" 0 "0" "0" TIMERSC CPUS
WDTPS TIMERSC CPUS
Bit 7 (WDTPS):
WDT time-out period select bit. 0 : 4.5 ms 1 : 18 ms
Bit 6 (TIMERSC): TCC, TCCA, TCCB, TCCC clock sources select 0/1 Fs/Fm* Fs: sub frequency for WDT internal RC time base 15kHz 30% Fm: main-oscillator clock Bit 5 (CPUS): CPU Oscillator Source Select 0 : sub-oscillator (fs) 1 : main oscillator (fosc) When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped. Bit 4 (IDLE): Idle Mode Enable Bit. From SLEP instruction, this bit will determine as to which mode to go. 0 : Idle="0"+SLEP instruction sleep mode 1 : Idle="1"+SLEP instruction idle mode
CPU Operation Mode
RESET Normal Mode fosc:oscillation fs: oscillation CPU: using fosc wake up
Wake up
IDLE="0" +SLEP SLEEP Mode fosc:stop fs: stop CPU: stop IDLE="0" + SLEP Wake up
CPUS="1"
CPUS="0"
IDLE="1" +SLEP IDLE="1 "+SLEP IDLE Mode fosc:stop fs: oscillation wake up CPU: stop
Green Mode fosc:stop fs: oscillation CPU: using fs
Figure 6-2 CPU Operation Mode
Bits 3 ~ 0:
These bits must set to "0" all the time.
26 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.2.22 IOCF1 (Pull-high Control Register)
Bit 7 /PH67 Bit 6 "1" Bit 5 "1" Bit 4 "1" Bit 3 "1" Bit 2 "1" Bit 1 "1" Bit 0 "1"
Note: The IOCD0 register is both readable and writable.
Bit 7 (/PH67): Control bit is used to enable the pull-high function of the P67 pin. 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 6 ~ 0: These bits must set to "1" all the time.
6.3 TCC/WDT and Prescaler
There are two 8-bit timers available as prescalers that can be extended to 16-bit timer for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PSW2 ~ PSW0 bits of the IOCE0 register are used to determine the prescaler of WDT. The prescaler timer is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler will be cleared by the "WDTC" and "SLEP" instructions. Figure 6-3 depicts the block diagram of TCC/WDT. TCC (R1) is an 8-bit timer. The TCC clock source can be internal clock (Fosc).
NOTE The internal TCC will stop running when in sleep mode. However, during AD conversion, when TCC is set to "SLEP" instruction, if the ADWE bit of the RE register is enabled, the TCC will keep on running.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or in sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10 IOCE0 (WDT Control and Interrupt Mask Registers 2). With no prescaler, the WDT time-out period is approximately 18ms or 4.5ms .
1 2
1
VDD=5V, WDT time-out period = 16.5ms 30% VDD=3V, WDT time-out period = 18ms 30% VDD=5V, WDT time-out period = 4.2ms 30% VDD=3V, WDT time-out period = 4.5ms 30% * 27
2
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Fosc/2 0 TCC Pin TE (CONT) 1 MUX 8 to 1 MUX Prescaler TS (CONT) PST2~0 (CONT) TCC overflow interrupt TCC (R1) Data Bus
8-Bit Counter (IOCC1)
WDT
8-Bit counter
8 to 1 MUX WDTE (IOCE0) WDT Time out
Prescaler
PSW2~0 (IOCE0)
Figure 6-3 TCC and WDT Block Diagram
6.4 I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain output set through software. Port 5 features an input status changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are illustrated in Figures 6-4, 6-5, and 6-6.
28 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
PCRD
Q Q
P R
D PCW R
_
C LK C L
PORT
Q Q
P R
D PDW R PDRD
IO D
_
C LK C L
0 1
M U X
Note: Pull-high and Open-drain are not shown in the figure.
Figure 6-4 I/O Port and I/O Control Register Circuit for Port 6 and Port 7
PCRD
Q Q
P R
D
_
CLK C L
PCWR
P50 ~ P57
PORT Q Q
P R
D
IOD PDWR
_
CLK C L
0 1
M U X
PDRD TI n
D
P R
Q Q
CLK C L
_
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-5 I/O Port and I/O Control Register Circuit for Ports 50~57
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 29
EM78P142
8-Bit Microprocessor with OTP ROM
I O C F.1
R F.1
TI 0 TI 1
TI 8
....
Figure. 6-6 Port 5 Block Diagram with Input Change Interrupt/Wake-up
6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function
(1) Wake-up (a) Before Sleep 1. Disable WDT 2. Read I/O Port 5 (MOV R5, R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction (b) After wake-up Next instruction (2) Wake-up and Interrupt (a) Before Sleep 1. Disable WDT 2. Read I/O Port 5 (MOV R5, R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Enable interrupt (Set IOCF ICIE =1) 6. Execute "SLEP" instruction (b) After wake-up 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction (3) Interrupt (a) Before Port 5 pin change 1. Read I/O Port 5 (MOV R5,R5) 2. Execute "ENI" or "DISI" 3. Enable interrupt (Set IOCF ICIE =1) (b) After Port 5 pin changed (interrupt) 1. IF "ENI" Interrupt vector (006H) 2. IF "DISI" Next instruction
30 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.5 Reset and Wake-up
6.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) The device is kept in reset condition for a period of approximately 18ms (except in LXT mode) after the reset is detected. When in LXT2 mode, the reset time is 500 ms. Two choices (18 ms or 4.5 ms ) are available for WDT-time out period. Once a reset occurs, the following functions are performed (the initial Address is 000h): The oscillator continues running, or will be started (if in sleep mode). The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper three bits of R3 is cleared The IOCB0 register bits are set to all "1" The IOCC0 register bits are set to all "1" The IOCD0 register bits are set to all "1" Bits 7, 5, and 4 of the IOCE0 register are cleared Bits 5 and 4 of the RE register are cleared RF and IOCF0 registers are cleared Executing the "SLEP" instruction will assert the sleep (power down) mode (When IDLE="0".). While entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and TCCC are stopped. The WDT (if enabled) is cleared but keeps on running. During AD conversion, when "SLEP" instruction is set; the Oscillator, TCC, TCCA, TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on running. The controller can be awakened by: Case 1 Case 2 Case 3
3
3 4 3
External reset input on /RESET pin WDT time-out (if enabled) Port 5 input status changes (if ICWE is enabled)
VDD=5V, Setup time period = 16.5ms 30%. VDD=3V, Setup time period = 18ms 30%. VDD=5V, Setup time period = 4.2ms 30%. VDD=3V, Setup time period = 4.5ms 30%. * 31
4
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Case 4 Case 5
AD conversion completed (if ADWE is enabled) Low Voltage Detector (if LVDWE is enabled)
The first two cases (1 and 2) will cause the EM78P142 to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3, 4, and 5 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from Address 0x06 (Case 3), 0x0C (Case 4), and 0x21 (Case 5) after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next to SLEP after wake-up. Only one of Cases 2 to 5 can be enabled before entering into sleep mode. That is: Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the EM78P142 can be awakened only with Case 1 or Case 2. Refer to the section on Interrupt (Section 6.6) for further details. Case [b] If Port 5 Input Status Change is used to wake up the EM78P142 and the ICWE bit of the RE register is enabled before SLEP, and WDT must be disabled. Hence, the EM78P142 can be awakened only with Case 3. Wake-up time is dependent on the oscillator mode. In RC mode, Wake-up time is 10s (for stable oscillators). In HXT2 (4 MHz) mode, Wake-up time is 800 s (for stable oscillators), and in LXT2 mode, Wake-up time is 2s ~ 3s. Case [c] If AD conversion completed is used to wake-up the EM78P142 and ADWE bit of RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P142 can be awakened only with Case 4. The wake-up time is 15 TAD (ADC clock period). Case[d] If Low voltage detector is used to wake-up the EM78P142 and the LVDWE bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P142 can be awakened only with Case 5. Wake-up time is dependent on the oscillator mode. If Port 5 Input Status Change Interrupt is used to wake up the EM78P142 (as in Case [b] above), the following instructions must be executed before SLEP:
BC MOV IOW WDTC MOV ENI (or DISI) MOV MOV MOV IOW SLEP R3, 6 A, @00xx1110b IOCE0 R5, R5 A, @xxxxxx1xb RE A, @xxxxxx1xb IOCF0 ; Select Segment 0 ; Select WDT prescaler and Disable WDT ; ; ; ; Clear WDT and prescaler Read Port 5 Enable (or disable) global interrupt Enable Port 5 input change wake-up bit
; Enable Port 5 input change interrupt ; Sleep
32 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM 6.5.1.1 Wake-up and Interrupt Modes Operation Summary
The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows.
Wake-up Signal Port 5 pin change Sleep Mode If enable ICWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction Idle Mode Green Mode Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Normal Mode Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction
If enable ICWE bit Wake-up + interrupt (if interrupt is enabled) + next instruction Wake-up + interrupt TCC overflow x (if interrupt is enabled) interrupt + next instruction If enable ADWE bit If enable ADWE bit AD Wake-up + interrupt Wake-up + interrupt conversion (if interrupt is enabled) (if interrupt is enabled) complete + next instruction + next instruction interrupt Fs and Fm don't stop Fs and Fm don't stop High-pulse Wake-up + interrupt width timer x (if interrupt is enabled) underflow + next instruction interrupt Low-pulse Wake-up + interrupt width timer x (if interrupt is enabled) underflow + next instruction interrupt Wake-up + interrupt TCCA x (if interrupt is enabled) overflow + next instruction interrupt TCCB Wake-up + interrupt x (if interrupt is enabled) overflow interrupt + next instruction TCCC Wake-up + interrupt x overflow (if interrupt is enabled) interrupt + next instruction If Enable LVDWE bit If Enable LVDWE bit Low Voltage Wake-up + interrupt Wake-up + interrupt Detector (if interrupt is enabled) (if interrupt is enabled) interrupt + next instruction + next instruction WDT Time out Low Voltage Reset After wake up: 1. If interrupt is enabled interrupt+ next instruction 2. If interrupt is disabled next instruction
Interrupt x (if interrupt is enabled) Fs and Fm don't stop or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Reset Reset Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction Reset Reset
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 33
EM78P142
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=0 Oscillator, TCC, TCCX and IR/PWM are stopped. Port 5 input status changed wake-up is invalid. RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=1 Set RF (ICIF)=1, Oscillator, TCC, TCCX and IR/PWM are stopped. Port 5 input status changed wake-up is invalid.
Idle Mode*
RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=0 TCC, TCCX and IR/PWM keep on running. Port5 input status changed wake-up is invalid. RE (ICWE) Bit 1=0, IOCF0 (ICIE) Bit 1=1 Set RF (ICIF)=1, TCC, TCCX and IR/PWM keep on running. Port5 input status changed wake-up is invalid. RE (ICWE) Bit 1=1, IOCF0 (ICIE) Bit1=0 Wake-up + Next Instruction TCC, TCCX and IR/PWM keep on running. RE (ICWE) Bit 1=1, DISI + IOCF0 (ICIE) Bit 1=1 Wake-up + Next Instruction + Set RF (ICIF)=1 TCC, TCCX and IR/PWM keep on running. RE (ICWE) Bit 1=1, ENI + IOCF0 (ICIE) Bit 1=1 Wake-up + Interrupt Vector (006H) + Set RF (ICIF)=1 TCC, TCCX and IR/PWM keep on running. DISI+IOCF0(TCIE) Bit 0 =1
Normal Mode
IOCF0 (ICIE) Bit 1=0
Green Mode
IOCF0 (ICIE) Bit 1=0
Port 5 input status Port 5 input status change change interrupted is interrupted is invalid invalid
NA
NA
NA
NA
Port 5 Input Status Change
RE (ICWE) Bit 1=1, IOCF0 (ICIE) Bit 1=0 Wake-up + Next Instruction Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ICWE) Bit1=1, DISI + IOCF0 (ICIE) Bit 1=1 Wake-up + Next Instruction + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ICWE) Bit 1=1, ENI + IOCF0 (ICIE) Bit 1=1 Wake-up + Interrupt Vector (006H) + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM are stopped.
NA
NA
NA
NA
DISI + IOCF0 (ICIE) Bit 1=1
DISI + IOCF0 (ICIE) Bit 1=1
Next Instruction + Set RF (ICIF)=1
Next Instruction + Set RF (ICIF)=1
ENI + IOCF0 (ICIE) Bit 1=1
ENI + IOCF0 (ICIE) Bit 1=1
Interrupt Vector(006H) + Set RF (ICIF)=1
Interrupt Vector(006H) + Set RF (ICIF)=1
DISI + IOCF0 (TCIE) Bit 0=1 Next Instruction + Set RF (TCIF)=1 ENI + IOCF0 (TCIE) Bit 0=1 Interrupt Vector (009H) + Set RF (TCIF)=1
DISI + IOCF0 (TCIE) Bit 0=1 Next Instruction + Set RF (TCIF)=1 ENI + IOCF0 (TCIE) Bit 0=1 Interrupt Vector (009H) + Set RF (TCIF)=1
TCC Overflow
NA
Wake-up + next instruction Set RF (TCIF)=1 ENI + IOCF0(TCIE) Bit 0 =1 Wake-up + Interrupt Vector (009H) + Set RF (TCIF)=1
34 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=0 Clear R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=1 Set RF (ADIF)=1, R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ADWE) Bit 3=1, IOCE0 (ADIE) Bit 5=0 Wake-up + Next Instruction,
Idle Mode*
RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=0 Clear R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. RE (ADWE) Bit 3=0, IOCE0 (ADIE) Bit 5=1 Set RF (ADIF)=1, R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM keep on running. RE (ADWE) Bit 3=1, IOCE0 (ADIE) Bit 5=0 Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed.
Normal Mode
IOCE0 (ADIE) Bit 5=0
Green Mode
IOCE0 (ADIE) Bit 5=0
AD conversion interrupted AD conversion is invalid interrupted is invalid
NA
NA
NA
NA
NA
NA
AD Conversion
Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. RE (ADWE) Bit 3=1, DISI + IOCE0 (ADIE) Bit 5=1 Wake-up + Next Instruction + RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed.
NA
NA
RE (ADWE) Bit 3=1, DISI + IOCE0 (ADIE) Bit 5=1
DISI + IOCE0 (ADIE) Bit 5=1
DISI + IOCE0 (ADIE) Bit 5=1
Wake-up + Next Instruction + RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. ENI + IOCE0 (ADIE) Bit 5=1 ENI + IOCE0 (ADIE) Bit 5=1 Next Instruction + RE (ADIF)=1 Next Instruction + RE (ADIF)=1
RE (ADWE) Bit 3=1, ENI RE (ADWE) Bit 3=1, ENI + + IOCE0 (ADIE) Bit 5=1 IOCE0 (ADIE) Bit 5=1 Wake-up + Interrupt Vector (00CH)+ RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. Wake-up + Interrupt Vector (00CH)+ RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed.
Interrupt Vector (00CH) + Set RE (ADIF)=1
Interrupt Vector (00CH) + Set RE (ADIF)=1
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 35
EM78P142
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
Idle Mode*
DISI + IOCF0 (HPWTIE) Bit 6=1 Wake-up +Next Instruction + Set RF (HPWTIF)=1
Normal Mode
DISI + IOCF0 (HPWTIE) Bit 6=1 Next Instruction + Set RF (HPWTIF)=1 ENI + IOCF0 (HPWTIE) Bit 6 =1 Interrupt Vector (012H) + Set RF (HPWTIF)=1 DISI + IOCF0 (LPWTIE) Bit 7=1 Next Instruction + Set RF (LPWTIF)=1 ENI + IOCF0 (LPWTIE) Bit 7 =1 Interrupt Vector (015H) + Set RF (LPWTIF)=1 DISI + IOCF0 (TCCAIE) Bit 3=1 Next Instruction + Set RF (TCCAIF)=1 ENI + IOCF0 (TCCAIE) Bit 3=1 Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) Bit 4=1 Next Instruction + Set RF (TCCBIF)=1 ENI + IOCF0 (TCCBIE) Bit 4=1
Green Mode
DISI + IOCF0 (HPWTIE) Bit 6=1 Next Instruction + Set RF (HPWTIF)=1 ENI + IOCF0 (HPWTIE) Bit 6 =1 Interrupt Vector (012H) + Set RF (HPWTIF)=1 DISI + IOCF0 (LPWTIE) Bit 7=1 Next Instruction + Set RF (LPWTIF)=1 ENI + IOCF0 (LPWTIE) Bit 7 =1 Interrupt Vector (015H) + Set RF (LPWTIF)=1 DISI + IOCF0 (TCCAIE) Bit 3=1 Next Instruction + Set RF (TCCAIF)=1 ENI + IOCF0 (TCCAIE) Bit 3=1 Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) Bit 4=1 Next Instruction + Set RF (TCCBIF)=1 ENI + IOCF0 (TCCBIE) Bit 4=1 Interrupt Vector (01BH) + Set RF (TCCBIF)=1 DISI + IOCF0 (TCCCIE) Bit 5=1 Next Instruction + Set RF (TCCCIF)=1 ENI + IOCF0 (TCCCIE) Bit 5=1 Interrupt Vector (01EH) + Set RF (TCCCIF)=1
IR/PWM underflow interrupt (High-pulse width timer underflow interrupt) NA
ENI + IOCF0 (HPWTIE) Bit 6 =1 Wake-up +Interrupt Vector (012H) + Set RF (HPWTIF)=1 DISI + IOCF0 (LPWTIE) Bit 7=1 Wake-up +Next Instruction + Set RF (LPWTIF)=1
IR/PWM underflow interrupt (Low-pulse width timer underflow interrupt)
NA
ENI + IOCF0 (LPWTIE) Bit 7 =1 Wake-up +Interrupt Vector (015H) + Set RF (LPWTIF)=1 DISI + IOCF0 (TCCAIE) Bit 3=1 Wake-up +Next Instruction + Set RF (TCCAIF)=1
TCCA Over Flow
NA
ENI + IOCF0 (TCCAIE) Bit 3=1 Wake-up +Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) Bit 4=1 Wake-up +Next Instruction
TCCB Over Flow
NA
+ Set RF (TCCBIF)=1 ENI + IOCF0 (TCCBIE) Bit 4=1
Interrupt Vector (01BH) Wake-up +Interrupt Vector (01BH) + Set RF(TCCBIF)=1 + Set RF (TCCBIF)=1 DISI + IOCF0 (TCCCIE) Bit 5=1 Wake-up +Next Instruction TCCC Over Flow + Set RF (TCCCIF)=1 NA ENI + IOCF0 (TCCCIE) Bit 5=1 Wake-up +Interrupt Vector (01EH) + Set RF (TCCCIF)=1 DISI + IOCF0 (TCCCIE) Bit 5=1 Next Instruction + Set RF (TCCCIF)=1 ENI + IOCF0 (TCCCIE) Bit 5=1 Interrupt Vector (01EH) + Set RF (TCCCIF)=1
36 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Signal
Sleep Mode
RE (LVDWE) Bit 0=0, IOCD1 (LVDIE) Bit 3=0 Low voltage detector wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit 0=0, IOCD1 (LVDIE) Bit 3=1 Set RE (LVDIF)=1, Low voltage detector wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit 0=1, IOCD1 (LVDIE) Bit 3=0 Wake-up + Next
Idle Mode*
Normal Mode
Green Mode
IOCD1 (LVDIE) Bit 3=0
RE (LVDWE) Bit 0=0, IOCD1 IOCD1 (LVDIE) Bit 3=0 (LVDIE) Bit 3=0 Low voltage detector wake-up is invalid. TCC, TCCX and IR/PWM keep on running. RE (LVDWE) Bit 0=0, IOCD1 (LVDIE) Bit 3=1 Set RE (LVDIF)=1, Low voltage detector wake-up is invalid. TCC, TCCX and IR/PWM keep on running. RE (LVDWE) Bit 0=1, IOCD1 (LVDIE) Bit 3=0 Wake-up + Next Instruction, TCC, TCCX and IR/PWM keep on running. NA NA NA
Low voltage detector interrupted is invalid.
Low voltage detector interrupted is invalid.
NA
NA
NA
NA
Low Voltage Instruction, Detector Oscillator, TCC, TCCX interrupt and IR/PWM are
stopped. RE (LVDWE) Bit =1, DISI + IOCD1 (LVDIE) Bit 3=1 Wake-up + Next Instruction + Set RE (LVDIF)=1, Oscillator, TCC, TCCX and IR/PWM are stopped. RE (LVDWE) Bit 2=1, ENI + IOCD1 (LVDIE) Bit 3=1
NA
RE (LVDWE) Bit 0=1, DISI + DISI + IOCD1 (LVDIE) IOCD1 (LVDIE) Bit 3=1 Bit 3=1
DISI + IOCD1 (LVDIE) Bit 3=1
Wake-up + Next Instruction + Set RE (LVDIF)=1, TCC, TCCX and IR/PWM keep on running.
Next Instruction + Set RE (LVDIF)=1
Next Instruction + Set RE (LVDIF)=1
RE (LVDWE) Bit0=1, ENI + IOCD1 (LVDIE) Bit 3=1
ENI + IOCD1 (LVDIE) Bit 3=1
ENI + IOCD1 (LVDIE) Bit 3=1
Wake-up + Interrupt Wake-up + Interrupt Vector Vector (021H) + Set RE (021H) + Set RE (LVDIF)=1, Interrupt Vector (021H) (LVDIF)=1,Oscillator, TCC, TCCX and IR/PWM + Set RE (LVDIF)=1 TCC, TCCX and keep on running. IR/PWM are stopped. WDT Timeout Wake-up + Reset IOCE (WDTE) (Address 0x00) Bit 7=1 Low voltage reset Wake-up + Reset (Address 0x00) Wake-up + Reset (Address 0x00) Wake-up + Reset (Address 0x00)
Interrupt Vector (021H) + Set RE (LVDIF)=1
Reset (Address 0x00)
Reset (Address 0x00)
Reset (Address 0x00)
Reset (Address 0x00)
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 37
EM78P142
8-Bit Microprocessor with OTP ROM
6.5.1.2
Register Initial Values after Reset
The following summarizes the initialized values for registers.
Address Name Reset Type
Bit Name Type NA IOC50 Power-on /RESET and WDT Wake-up from Pin Change Bit Name Type NA IOC60 Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on NA IOC70 /RESET and WDT Wake-up from Pin Change Bit Name Power-on NA IOC80 /RESET and WDT Wake-up from Pin Change Bit Name Power-on NA IOC90 /RESET and WDT Wake-up from Pin Change Bit Name NA IOCA0 (IRCR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name NA IOCB0 (PDCR) Power-on /RESET and WDT Wake-up from Pin Change
Bit 7
- 1 1 P 1 C67 1 1 P 1
x
Bit 6
- 1 1 P 1 - 1 1 P 1
x
Bit 5
C55 1 1 P 1 - 1 1 P 1
x
Bit 4
- 1 1 P 1 - 1 1 P 1
x
Bit 3
C53 1 1 P 1 - 1 1 P 1
x
Bit 2
C52 1 1 P 1 - 1 1 P 1
x
Bit 1
C51 1 1 P 1 - 1 1 P 1 C71 1 1 P - 0 0 P - 0 0 P LGP 0 0 P /PD51 1 1 P
Bit 0
C50 1 1 P 1 - 1 1 P 1 C70 1 1 P - 0 0 P - 0 0 P IROUTE 0 0 P /PD50 1 1 P
0 0 P
x
0 0 P
x
0 0 P - 0 0 P - 0 0 P
0 0 P - 0 0 P - 0 0 P
0 0 P - 0 0 P
x
0 0 P TCCAEN 0 0 P TCCCEN 0 0 P HF 0 0 P /PD52 1 1 P
0 0 P
0 0 P
TCCBHE TCCBEN 0 0 P 0 0 P
0 0 P IRE 0 0 P /PD53 1 1 P
TCCCSE TCCCS2 TCCCS1 TCCCS0 0 0 P - 1 1 P 0 0 P - 1 1 P 0 0 P /PD55 1 1 P 0 0 P - 1 1 P
38 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
Bit 7
/OD67 1 1 P - 1 1 P WDTC 0 0 P
Bit 6
- 1 1 P - 1 1 P - 0 0 P
Bit 5
- 1 1 P /PH55 1 1 P ADIE 0 0 P
Bit 4
- 1 1 P - 1 1 P - 0 0 P
Bit 3
- 1 1 P /PH53 1 1 P PSWE 0 0 P
Bit 2
- 1 1 P /PH52 1 1 P PSW2 0 0 P - 0 0 P TCCA2 0 0 P TCCB2 0 0 P
Bit 1
- 1 1 P /PH51 1 1 P PSW1 0 0 P ICIE 0 0 P TCCA1 0 0 P TCCB1 0 0 P
Bit 0
- 1 1 P /PH50 1 1 P PSW0 0 0 P TCIE 0 0 P TCCA0 0 0 P TCCB0 0 0 P
NA
IOCC0 (ODCR)
NA
IOCD0 (PHCR1)
NA
IOCE0
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE 0 0 P TCCA7 0 0 P TCCB7 0 0 P 0 0 P TCCA6 0 0 P TCCB6 0 0 P 0 0 P TCCA5 0 0 P TCCB5 0 0 P 0 0 P TCCA4 0 0 P TCCB4 0 0 P 0 0 P TCCA3 0 0 P TCCB3 0 0 P
NA
IOCF0
/RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-p from Pin Change
NA
IOC51 (TCCA)
NA
IOC61 (TCCB)
TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0 0 0 P TCCC7 0 0 P LTR7 0 0 P 0 0 P TCCC6 0 0 P LTR6 0 0 P 0 0 P TCCC5 0 0 P LTR5 0 0 P 0 0 P TCCC4 0 0 P LTR4 0 0 P 0 0 P TCCC3 0 0 P LTR3 0 0 P 0 0 P TCCC2 0 0 P LTR2 0 0 P 0 0 P TCCC1 0 0 P LTR1 0 0 P 0 0 P TCCC0 0 0 P LTR0 0 0 P
NA
IOC71 (TCCBH)
NA
IOC81 (TCCC)
NA
IOC91 (LTR)
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 39
EM78P142
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name
Bit 7
HTR7 0 0 P HTSE 0 0 P
Bit 6
HTR6 0 0 P HTS2 0 0 P
Bit 5
HTR5 0 0 P HTS1 0 0 P
Bit 4
HTR4 0 0 P HTS0 0 0 P
Bit 3
HTR3 0 0 P LTSE 0 0 P
Bit 2
HTR2 0 0 P LTS2 0 0 P
Bit 1
HTR1 0 0 P LTS1 0 0 P
Bit 0
HTR0 0 0 P LTS0 0 0 P
NA
IOCA1 (HTR)
NA
IOCB1 (HLTS)
TCCPC7 TCCPC6 TCCPC5 TCCPC4 TCCPC3 TCCPC2 TCCPC1 TCCPC0 0 0 P TYPE1 1 P P 0 0 P TYPE0 1 P P 0 0 P LVR1 1 P P 0 0 P LVR0 1 P P IDLE 1 1 P - 1 1 P - 1 1 P - U P P - 0 0 P 0 0 P LVDIE 0 0 P - 0 0 P - 1 1 P PSTE 0 0 P - U P P - 0 0 P 0 0 P LVDEN 0 P P - 0 0 P - 1 1 P PST2 0 0 P - U P P - 0 0 P 0 0 P LVD1 1 1 P - 0 0 P - 1 1 P PST1 0 0 P - U P P - 0 00 P 0 0 P LVD0 1 1 P - 0 0 P - 1 1 P PST0 0 0 P - U P P - 0 0 P
NA
IOCC1 (TCCPC)
NA
Power-on IOCD1 (LVD CR) /RESET and WDT (ROMLESS) Wake-up from Pin Change HS1 Power-on IOCE1 (HSC) /RESET and WDT (ROMLESS) Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
WDPTS TIMERSC CPUS 1 P P /PH67 1 1 P - 1 1 P - U P P - 0 0 P 1 1 P - 1 1 P INT 0 0 P - U P P - 0 0 P 1 1 P - 1 1 P - 1 1 P - U P P - 0 0 P
NA
NA
IOCF1 (PHCR2)
NA
CONT
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x00
R0 (IAR)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x01
R1 (TCC)
/RESET and WDT Wake-up from Pin Change
40 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on
Bit 7
- 0 0
Bit 6
- 0 0
Bit 5
- 0 0
Bit 4
- 0 0
Bit 3
- 0 0
Bit 2
- 0 0
Bit 1
- 0 0
Bit 0
- 0 0
0x02
R2 (PC)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
Jump to Address 0x06 or continue to execute next instruction RST 0 0 P
x
IOCS 0 0 P BS 0 0 P - 1 1 P - 1 1 P - 0 0 P ADE6 0 0 0 CKR1 0 0 P SIGN 0 0 P
- 0 0 P - U P P P55 1 1 P - 1 1 P - 0 0 P ADE5 0 0 0 CKR0 0 0 P VOF[2] 0 0 P
T 1 T T - U P P - 1 1 P - 1 1 P - 0 0 P ADE4 0 0 0 ADRUN 0 0 P VOF[1] 0 0 P
P 1 t t - U P P P53 1 1 P - 1 1 P - 0 0 P ADE3 0 0 P ADPD 0 0 P VOF[0] 0 0 P
Z U P P - U P P P52 1 1 P - 1 1 P - 0 0 P ADE2 0 0 P ADIS2 0 0 0 - 0 0 P
DC U P P - U P P P51 1 1 P - 1 1 P P71 1 1 P ADE1 0 0 P ADIS1 0 0 P - 0 0 P
C U P P - U P P P50 1 1 P - 1 1 P P70 1 1 P ADE0 0 0 P ADIS0 0 0 P - 0 0 P
0x03
R3 (SR)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0 0 0 - 1 1 P P67 1 1 P - 0 0 P - 0 0 0 - 0 0 P CALI 0 0 P
0x04
R4 (RSR)
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x05
R5
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x06
R6
/RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x7
R7
/RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on /RESET and WDT Wake-up from Pin Change
0x8
R8 (AISR)
0x9
R9 (ADCON)
0xA
RA (ADOC)
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 41
EM78P142
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name
Bit 7
AD11 U U P "0" 0 0 0 AD7 U U P /LVD 0 0 P
Bit 6
AD10 U U P "0" 0 0 0 AD6 U U P LVDIF 0 0 P
Bit 5
AD9 U U P "0" 0 0 0 AD5 U U P ADIF 0 0 P
Bit 4
AD8 U U P "0" 0 0 0 AD4 U U P - 0 0 P
Bit 3
AD7 U U P AD11 U U P AD3 U U P ADWE 0 0 P
Bit 2
AD6 U U P AD10 U U P AD2 U U P - 0 0 P - 0 0 P - U P P
Bit 1
AD5 U U P AD9 U U P AD1 U U P ICWE 0 0 P ICIF 0 0 P - U P P
Bit 0
AD4 U U P AD8 U U P AD0 U U P LVDWE 0 0 P TCIF 0 0 P - U P P
0XB
RB (ADDATA)
0XC
Power-on RC (ADDATA1H) /RESET and WDT Wake-up from Pin Change Bit Name Power-on RD (ADDATA1L) /RESET and WDT Wake-up from Pin Change Bit Name
0XD
0xE
RE (ISR2)
Power-on /RESET and WDT Wake-up from Pin Change Bit Name
LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P
0xF
RF (ISR1)
Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on
0x10~0x3F
R10~R3F
/RESET and WDT Wake-up from Pin Change
Legend: "x" = not used "u" = unknown or don't care
"P" = previous value before reset "t" = check "Reset Type" Table in Section 6.5.2
42 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.5.1.3
Controller Reset Block Diagram
VDD D Q CLK CLR CLK
Oscillator
Power-on Reset Voltage Detector
ENWDTB WDT Timeout WDT Setup time Reset
/RESET
Figure 6-7 Controller Reset Block Diagram
6.5.2 The T and P Status under Status Register
A reset condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled) The values of T and P as listed in the table below, are used to check how the processor wakes up.
Reset Type Power-on /RESET during Operating mode, /RESET wake-up during Sleep mode LVR during Operating mode, LVR wake-up during Sleep mode WDT during Operating mode WDT wake-up during Sleep mode Wake-up on pin change during Sleep mode RST 0 0 0 0 0 0 0 1 T 1 *P 1 *P 1 0 0 1 P 1 *P 0 *P 0 1 0 0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event Power-on WDTC instruction WDT time-out SLEP instruction Wake-up on pin changed during Sleep mode RST 0 *P 0 *P 1 T 1 1 0 1 1 P 1 1 *P 0 0
*P: Previous value before reset Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 43
EM78P142
8-Bit Microprocessor with OTP ROM
6.6 Interrupt
The EM78P142 has five interrupts enumerated below: 1. TCC, TCCA, TCCB, TCCC overflow interrupt 2. Port 5 Input Status Change Interrupt 3. Analog to Digital conversion completed 4. IR/PWM underflow interrupt 5. Low voltage detector interrupt Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV R5, R5") is necessary. Each Port 5 pin will have this feature if its status changes. The Port 5 Input Status Change Interrupt will wake up the EM78P142 from sleep mode if it is enabled prior to going into sleep mode by executing SLEP instruction. When wake up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. If enabled, the global interrupt will branch out to the Interrupt Vector 006H. RF and RE are the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. When interrupt mask bits is "Enable", the flag in the Interrupt Status Register (RF) is set regardless of the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0 (refer to figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the ENI execution). When an interrupt is generated by the Timer clock (when enabled), the next instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB, and TCCC respectively). When an interrupt generated by the AD conversion is completed (when enabled), the next instruction will be fetched from Address 00CH When an interrupt is generated by the High time / Low time down counter underflow (when enabled), the next instruction will be fetched from Addresses 012 and 015H (High time and Low time respectively). When an interrupt is generated by the Low Voltage Detect (when enabled), the next instruction will be fetched from Address 021 (Low Voltage Detector interrupt). Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4 registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and R4 will be replaced by the new interrupt. After an interrupt service routine is completed, the ACC, R3, and R4 registers are restored.
44 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
VCC
D /IRQn
P R C L
Q _ Q RFRD
IRQn INT IRQm ENI/DISI
CLK RF
Q _ Q
P R C L
D CLK IOCFWR
IOD
IOCF /RESET
IOCFRD
RFWR
Interrupt sources ENI/DISI
ACC R3 (7~5, 2~0) R4 (6~0)
Interrupt occurs RETI
Stack ACC Stack R3 Stack R4
Figure 6-8 Interrupt Back-up Diagram
In EM78P142, each individual interrupt source has its own interrupt vector as depicted in the table below.
Interrupt Vector 003H 006H 009H 00CH 00FH 012H 015H 018H 01BH 01EH 021H Port 5 pin change TCC overflow interrupt AD conversion complete interrupt NA High-pulse width timer underflow interrupt Low-pulse width timer underflow interrupt TCCA overflow interrupt TCCB overflow interrupt TCCC overflow interrupt Low Voltage Detector interrupt Interrupt Status NA Priority* - 2 3 4 - 5 6 7 8 9 1
Note: *Priority: 1 = highest ; 9 = lowest priority
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 45
EM78P142
8-Bit Microprocessor with OTP ROM
6.7 Analog-To-Digital Converter (ADC)
The analog-to-digital circuitry consists of an 8-bit analog multiplexer; three control registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA1/RB, ADDATA1H/RC, and ADDATA1L/RD) and an ADC with 12-bit resolution as shown in the functional block diagram below. The analog reference voltage (Vref) and the analog ground are connected via separate input pins. The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and ADDATA1L. Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS1 and ADIS0.
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Fsco 4-1 MUX Internal RC 7~0 AISR 1 ADCON 0 6 ADCON DATA BUS 5 RF 3 11 10 9 8 7 6 5 4 3 2 1 0 4 ADCON 3 Vref
ADC ( successive approximation )
Power-Down Start to Convert
ADDATA1H
ADDATA1L
Figure 6-9 Analog-to-Digital Conversion Functional Block Diagram
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
6.7.1.1
Bit 7 "0"
R8 (AISR: ADC Input Select Register)
Bit 6 ADE6 Bit 5 ADE5 Bit 4 ADE4 Bit 3 ADE3 Bit 2 ADE2 Bit 1 ADE1 Bit 0 ADE0
The AISR register individually defines the P5, P6 and P7 pins as analog inputs or as digital I/O. Bit 7: Bit 6 (ADE6): This bit must be set to "0" all the time. AD converter enable bit of P55 pin 0 : Disable ADC6, P55 functions as I/O pin 1 : Enable ADC6 to function as analog input pin Bit 5 (ADE5): AD converter enable bit of P70 pin 0 : Disable ADC5, P70 functions as I/O pin 1 : Enable ADC5 to function as analog input pin
46 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Bit 4 (ADE4):
AD converter enable bit of P67 pin 0 = Disable ADC4, P67 functions as I/O pin 1 = Enable ADC4 to function as analog input pin
Bit 3 (ADE3):
AD converter enable bit of P53 pin 0 = Disable ADC3, P53 functions as I/O pin 1 = Enable ADC3 to function as analog input pin
Bit 2 (ADE2):
AD converter enable bit of P52 pin 0 = Disable ADC2, P53 functions as I/O pin 1 = Enable ADC2 to function as analog input pin
Bit 1 (ADE1):
AD converter enable bit of P51 pin 0 = Disable ADC1, P51 acts as I/O pin 1 = Enable ADC1 acts as analog input pin
Bit 0 (ADE0):
AD converter enable bit of P50 pin 0 = Disable ADC0, P50 functions as I/O pin 1 = Enable ADC0 to function as analog input pin
6.7.1.2
Bit 7 "0"
R9 (ADCON: ADC Control Register)
Bit 6 CKR1 Bit 5 CKR0 Bit 4 ADRUN Bit 3 ADPD Bit 2 ADIS2 Bit 1 ADIS1 Bit 0 ADIS0
The ADCON register controls the operation of the AD conversion and decides which pin should be currently active. Bit 7: This bit must be set to "0" all the time Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The prescaler of ADC oscillator clock rate 00 = 1: 16 (default value) 01 = 1: 4 10 = 1: 64 11 = 1: 8
CPUS 1 1 1 1 0 CKR1: CKR0 Operation Mode Max. Operation Frequency 00 01 10 11 xx Fosc/16 Fosc/4 Fosc/64 Fosc/8 Internal RC 4 MHz 1 MHz 16 MHz 2 MHz -
Bit 4 (ADRUN): ADC starts to RUN 0 : reset upon completion of the conversion. This bit cannot be reset though software. 1 : an AD conversion is started. This bit can be set by software.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 47
EM78P142
8-Bit Microprocessor with OTP ROM
Bit 3 (ADPD):
ADC Power-down mode 0 : switch off the resistor reference to conserve power even while the CPU is operating 1 : ADC is operating
Bit 2 ~ Bit 0 (ADIS2 ~ ADIS0): Analog Input Select 000 = ADIN0/P50 001 = ADIN1/P51 010 = ADIN2/P52 011 = ADIN3/P53 100 = ADIN4/P67 101 = ADIN5/P70 110 = ADIN6/P55 111 = not used These bits can only be changed when the ADIF bit and the ADRUN bit are both LOW 6.7.1.3
Bit 7 CALI
RA (ADOC: AD Offset Calibration Register)
Bit 6 SIGN Bit 5 VOF[2] Bit 4 VOF[1] Bit 3 VOF[0] Bit 2 "0" Bit 1 "0" Bit 0 "0"
Bit 7 (CALI): Calibration enable bit for ADC offset 0 = disable Calibration 1 = enable Calibration Bit 6 (SIGN): Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits.
VOF[2] 0 0 0 0 1 1 1 1 VOF[1] 0 0 1 1 0 0 1 1 VOF[0] 0 1 0 1 0 1 0 1
EM78P142
ICE341N 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
Bit 2 ~ Bit 0: Unimplemented, read as `0'.
48 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
6.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of the AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2s for each K of the analog source impedance and at least 2s for the low-impedance source. The maximum recommended impedance for analog source is 10K at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started.
6.7.4 AD Conversion Time
CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at the maximum frequency without sacrificing the AD conversion accuracy. For the EM78P142, the conversion time per bit is about 4s. The table below shows the relationship between Tct and the maximum operating frequencies.
CKR1:CKR0 00 01 10 11 Operation Mode Fosc/16 Fosc/4 Fosc/64 Fosc/8 Max. Operation Max. Conversion Frequency Rate/Bit 4 MHz 1 MHz 16 MHz 2 MHz 250kHz (4s) 250kHz (4s) 250kHz ( 4s) 250kHz ( 4s) Max. Conversion Rate 15x4s=60s (16.7kHz) 15x4s=60s (16.7kHz) 15x4s=60s (16.7kHz) 15x4s=60s (16.7kHz)
NOTE Pin not used as an analog input pin can be used as regular input or output pin. During conversion, do not perform output instruction to maintain precision for all of the pins.
6.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillator, TCC, TCCA, TCCB, TCCC, and AD conversion.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 49
EM78P142
8-Bit Microprocessor with OTP ROM
The AD Conversion is considered completed as determined by: 1. The ADRUN bit of the R9 register is cleared to "0". 2. The ADIF bit of the RE register is set to "1". 3. The ADWE bit of the RE register is set to "1." Wakes up from ADC conversion (where it remains in operation during sleep mode). 4. Wake up and execution of the next instruction if the ADIE bit of the IOCE0 is enabled and the "DISI" instruction is executed. 5. Wake up and enters into Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is enabled and the "ENI" instruction is executed. 6. Enters into Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is enabled and the "ENI" instruction is executed. The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the AD conversion will be shut off, no matter what the status of the ADPD bit is.
6.7.6 Programming Process/Considerations
6.7.6.1 Programming Process
Follow these steps to obtain data from the ADC: 1. Write to the eight bits (ADE7: ADE0) on the R8 (AISR) register to define the characteristics of R5 (digital I/O, analog channels, or voltage reference pin) 2. Write to the R9/ADCON register to configure the AD module: a) Select the ADC input channel ( ADIS2 : ADIS0 ) b) Define the AD conversion clock rate ( CKR1 : CKR0 ) c) Select the VREFS input source of the ADC d) Set the ADPD bit to 1 to begin sampling 3. Set the ADWE bit, if the wake-up function is employed 4. Set the ADIE bit, if the interrupt function is employed 5. Write "ENI" instruction, if the interrupt function is employed 6. Set the ADRUN bit to 1 7. Write "SLEP" instruction or Polling. 8. Wait for wake-up or for the ADRUN bit to be cleared to "0" , interrupt flag (ADIF) is set "1," or ADC interrupt occurs. 9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the ADC input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L values can be cleared to `0'.
50 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
10. Clear the interrupt flag bit (ADIF). 11. For next conversions, go to Step 1 or Step 2 as required. At least two Tct is required before the next acquisition starts.
NOTE In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins during AD conversion
6.7.6.2
Sample Demo Programs ; Indirect addressing register ; Status register
R_0 == 0 PSW == 3 PORT5 == 5 PORT6 == 6 R_E== 0XE
; Interrupt status register
B. Define a Control Register IOC50 == 0X5 IOC60 == 0X6 IOCE0== 0XE C_INT== 0XF ; ; ; ; Control Register of Port 5 Control Register of Port 6 Interrupt Mask Register 2 Interrupt Mask Register
C. ADC Control Register ADDATA == 0xB AISR == 0x08 ADCON == 0x9 ; The contents are the results of ADC ; ADC input select register ;7 6 5 4 3 2 1 0 ;CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
D. Define Bits in ADCON ADRUN == 0x4 ADPD == 0x3 E. Program Starts ORG 0 JMP INITIAL ; Initial address ; ; ADC is executed as the bit is set ; Power Mode of ADC
ORG 0x0C ; Interrupt vector JMP CLRRE ; ;(User program section) ; CLRRE: MOV A,RE AND A, @0BXX0XXXXX ; To clear the ADIF bit, "X" by application MOV RE,A BS ADCON, ADRUN ; To start to execute the next AD conversion ; if necessary RETI
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 51
EM78P142
8-Bit Microprocessor with OTP ROM
INITIAL: MOV A,@0B00000001 MOV AISR,A MOV A,@0B00001000 MOV ADCON,A
; To define P50 as an analog input ; To select P50 as an analog input channel, and AD power on ; To define P50 as an input pin and set clock rate at fosc/16
En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others ; are dependent on applications IOW PORT5 MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, "X" ; by application MOV RE,A MOV A, @0BXX1XXXXX ; Enable the ADIE interrupt function of ADC, ; "X" by application IOW IOCE0 ENI ; Enable the interrupt function BS ADCON, ADRUN ; Start to run the ADC
; If the interrupt function is employed, the following three lines may be ignored ;If Sleep: SLEP ; ;(User program section) ; or ;If Polling: POLLING: JBC ADCON, ADRUN JMP POLLING
; To check the ADRUN bit continuously; ; ADRUN bit will be reset as the AD conversion ; is completed
; ;(User program section)
52 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.8 Infrared Remote Control Application/PWM Waveform Generation
6.8.1 Overview
This LSI can easily output infrared carrier or PWM standard waveform. As illustrated below, the IR and PWM waveform generation function include an 8-bit down count timer/counter, high-time, low-time, and IR control register. The IROUT pin waveform is determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high-time rate, low-time rate control register), IOC81 (TCCC timer), IOCA1 (high-time register), and IOC91 (low-time register).
Fosc
8-bit counter 8-bit counter Scale (IOCA0) Scale (IOCB 1) 8-to-1 MUX 8
8-bit counter Scale (IOCB1)
8-to-1 MUX
8-to-1 MUX
Auto-reload buffer (High-time)(IOCA1)
8-bit binary down counter 8
8-bit binary down counter 8
8
Auto-reload buffer (Low-time) (IOC91)
Fcarrier
8-bit binary down counter 8 Auto-reload buffer (TCCC)(IOC81)
H/W Modulator
HF
LGP
IRE
IROUT pin
Underflow Interrupt HPWTIF LPWTIF
Figure 6-10 IR/PWM System Block Diagram
Details of the Fcarrier High Time Width and Low Time Width are shown below:
Fcarrier = 2
where
{ [ 1 + Decimal TCCC Value (IOC81) ] x TCCC Scale (IOCA0)}
FOSC 1
FT
FT =
High Time Width = Low Time Width =
{ [ 1 + Decimal High Time Value (IOCA1)] x High Time Scale (IOCB1) } { [ 1 + Decimal Low Time Value (IOC91)] x Low Time Scale (IOCB1) }
FT FT
When an interrupt is generated by the High time down counter underflow (when enabled), the next instruction will be fetched from Address 018 and 01BH (High time and Low time respectively).
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 53
EM78P142
8-Bit Microprocessor with OTP ROM
6.8.2 Function Description
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low-time segments of the pulse.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE IROUT
Figure 6-11a LGP=0, HF=1, IROUT Pin Output Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is determined by the high time width and low time width instead. This mode can produce standard PWM waveform.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE IROUT
Figure 6-11b LGP=0, HF=0, IROUT Pin Output Waveform
54 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low-time segments of the pulse. When IRE goes low from high, the output waveform of IROUT will keep transmitting until high-time interrupt occurs.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start
IRE IROUT
IR disable Always high-level
Figure 6-11c LGP=0, HF=1, When IRE goes Low from High, IROUT Pin Outputs Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is determined by high time width and low time width. This mode can produce standard PWM waveform when IRE goes low from high. The output waveform of IROUT will keep on transmitting until high-time interrupt occurs.
Fcarrier
low time width
high time width
low time width
high time width
HF
Start IRE IR disable
IROUT
Always high-level
Figure 6-11d LGP=0, HF=0, When IRE goes Low from High, Irout Pin Output Waveform
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 55
EM78P142
8-Bit Microprocessor with OTP ROM
The following figure shows LGP=1 and HF=1. When this bit is set to high level, the high-time segment of the pulse is ignored. So, IROUT waveform output is determined by low-time width.
Fcarrier
low time width
low time width
low time width
HF
Start
IRE IROUT
IR disable
Always high-level
Figure 6-11e LGP=1 and HF=1, IROUT Pin Output Waveform
6.8.3 Programming the Related Registers
When defining IR/PWM, refer to the operation of the related registers as shown in the tables below. IR/PWM Related Control Registers
Address
0x09 0X0A 0x0F 0X0B
Name
IOC90
Bit 7
Bit 6
Bit 5
"0"
Bit 4
"0"
Bit 3
"0" IRE/0
Bit 2
TCCCEN/0 HF/0 "0" LTS2/0
Bit 1
"0" LGP/0 ICIE/0 LTS1/0
Bit 0
"0" IROUTE/0 TCIE/0 LTS0/0
TCCBHE/0TCCBEN/0
IR CR TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0 /IOCA0 IMR /IOCF0 HLTS /IOCB1
LPWTIE/0 HPWTIE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0 HTSE/0 HTS2/0 HTS1/0 HTS0/0 LTSE/0
IR/PWM Related Status/Data Registers
Address
0x0F 0x06 0X09 0X0A
Name
ISR/RF TCCC /IOC81 LTR /IOC91 HTR /IOCA1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
"0"
Bit 1
ICIF/0
Bit 0
TCIF/0
LPWTIF/0 HPWTIF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0 LTR7/0 HTR7/0 LTR6/0 HTR6/0 LTR5/0 HTR5/0 LTR4/0 HTR4/0 LTR3/0 HTR3/0 LTR2/0 HTR2/0 LTR1/0 HTR1/0 LTR0/0 HTR0/0
56 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.9 Timer
6.9.1 Overview
Timer A (TCCA) is an 8-bit clock timer. Timer B (TCCB) is a 16-bit clock timer. Timer C (TCCC) is an 8-bit clock timer that can be extended to 16-bit clock timer with programmable scalers. TCCA, TCCB, and TCCC can be read and written to, and are cleared at every reset condition.
6.9.2 Function Description
Set predict value TCCAEN Set TCCAIF TCCA Overflow Fosc Fosc TCCB Overflow 8-to-1 MUX Set predict value TCCBEN Set TCCBIF TCCC Overflow TCCCS1 ~ TCCCS0 Set predict value TCCCEN Set TCCCIF
8 Bit counter
Fosc
Figure 6-12 Timer Block Diagram
Each signal and block of the above Timer block diagram is described as follows: TCCX: Timer A~C register. TCCX is incremented until it matches with zero, and then reloads the predicted value. When writing a value to TCCX, the predicted value and TCCX value become the set value. When reading from TCCX, the value will be the TCCX direct value. When TCCXEN is enabled, the reloading of the predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at the same time. It is an up timer. TCCA Timer (IOC51): IOC51 (TCCA) is an 8-bit clock timer. It can be read, written to, and cleared on any reset condition and it is also an Up Timer.
TCCA Timeout period =
TCCB Timer (IOC61):
FOSC x 256 - TCCA cnt x 1
(
1
)
IOC61 is an 8-bit clock timer for the least significant byte of TCCBX (TCCB). It can be read, written, and cleared on any reset condition and it is also an Up Timer.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 57
EM78P142
8-Bit Microprocessor with OTP ROM
TCCBH / MSB Timer (IOC71): IOC71 is an 8-bit clock timer for the most significant byte of TCCBX (TCCBH). It can be read, written to, and cleared on any reset condition. When TCCBHE (IOC90) is "0," then TCCBH is disabled. When TCCBHE is"1," then TCCB is a 16-bit length timer. When TCCBH is disabled:
TCCB Timeout period =
When TCCBH is enabled:
FOSC x 256 - TCCB cnt x 1
(
1
)
TCCB Timeout period =
TCCC Timer (IOC81):
FOSC x
[ 65536
- TCCBH x 256 + TCCB cnt x 1
(
1
)
]
IOC81 (TCCC) is an 8-bit clock timer. It can be read, written to, and cleared on any reset condition. If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC timer scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Figure 6-11 in Section 6.8.2, Function Description). The TCCC value will then be the TCCC predicted value. When HF = 0 or IRE = 0. The TCCC is an Up Timer. In TCCC Up Timer mode:
TCCC Timeout period =
1
FOSC x Scaler (IOCA0 ) x 256 - TCCC cnt x 1
(
)
When HF = 1 and IRE = 1, TCCC timer scale uses the low-time segments of the pulse generated by the Fcarrier frequency modulation. In IR mode:
Fcarrier = 2
{ [ 1 + Decimal TCCC Value (IOC81) ] x TCCC Scale (IOCA0)}
where
FT
FT =
FOSC 1
58 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.9.3 Programming the Related Registers
When defining TCCX, refer to the operation of its related registers as shown in the tables below. TCCX Related Control Registers:
Address
0x08 0x09 0x0A 0x0F
Name
IOC80 IOC90 IR CR /IOCA0 IMR /IOCF0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
"0" "0"
Bit 3
"0" "0"
IRE/0 TCCAIE/0
Bit 2
TCCAEN/0 TCCCEN/0 HF/0
Bit 1
"0" "0"
LGP/0 ICIE/0
Bit 0
"0" "0"
IROUTE/0 TCIE/0
TCCBHE/0 TCCBEN/0
"0"
TCCCSE/0 TCCCS2/0 TCCCS1/0 TCCCS0/0 LPWTE/0 HPWTE/0 TCCCIE/0 TCCBIE/0
"0"
Related TCCX Status/Data Registers:
Address
0x0F 0x05 0x06 0x07 0x08
Name
ISR/RF TCCA /IOC51 TCCB /IOC61 TCCBH /IOC71 TCCC /IOC81
Bit 7
LPWTF/0 TCCA7/0 TCCB7/0
Bit 6
HPWTF/0 TCCA6/0 TCCB6/0
Bit 5
TCCCIF/0 TCCA5/0 TCCB5/0
Bit 4
TCCBIF/0 TCCA4/0 TCCB4/0
Bit 3
TCCAIF/0 TCCA3/0 TCCB3/0
Bit 2
"0"
TCCA2/0 TCCB2/0
Bit 1
ICIF/0 TCCA1/0 TCCB1/0
Bit 0
TCIF/0 TCCA0/0 TCCB0/0
TCCBH7/0 TCCBH6/0 TCCBH5/0 TCCBH4/0 TCCBH3/0 TCCBH2/0 TCCBH1/0 TCCBH0/0 TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 59
EM78P142
8-Bit Microprocessor with OTP ROM
6.10 Oscillator
6.10.1 Oscillator Modes
The EM78P142 can be operated in six different oscillator modes, such as High Crystal Oscillator Mode 1 (HXT1), High Crystal Oscillator Mode 2 (HXT2), Low Crystal Oscillator Mode 1 (LXT1), Low Crystal Oscillator Mode 2 (LXT2), External RC Oscillator Mode (ERC), and RC Oscillator Mode with Internal RC Oscillator Mode (IRC). You can select one of them by programming the OSC2, OCS1, and OSC0 in the Code Option register. The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.
Oscillator Modes
ERC (External RC oscillator mode); P70/OSCO acts as P70 ERC (External RC oscillator mode); P70/OSCO acts as OSCO IRC (Internal RC oscillator mode); P70/OSCO acts as P70 IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO LXT1 (Frequency range of XT mode is 1MHz ~ 100kHz) HXT1 (Frequency range of XT mode is 16 MHz ~ 6 MHz) LXT2 (Frequency range of XT mode is 32kHz) HXT2 (Frequency range of XT mode is 6 MHz ~ 1 MHz) (default)
1 2 3 3 3 3 3 2 2 1 1
OSC2
0 0 0 0 1 1 1 1
OSC1
0 0 1 1 0 0 1 1
OSC0
0 1 0 1 0 1 0 1
In ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4. In IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option Word 0 Bit 6 ~ Bit 4. In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot and should not be defined as normal I/O pins.
The maximum operating frequency limit of crystal/resonator at different VDDs, are as follows:
Conditions VDD
2.1V Two clocks 3.0V 4.5V
Max. Freq. (MHz)
4 8 16
60 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.10.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P142 can be driven by an external clock signal through the OSCI pin as illustrated below.
OSCI
OSCO
Figure 6-13 External Clock Input Circuit
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Figure 6-14 below depicts such a circuit. The same applies to the HXT1 mode, HTX2 mode, LXT1 mode and LXT2 mode.
C1 OSCI Crystal
OSCO RS C2
Figure 6-14 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, user should refer to the resonator specifications for the appropriate values of C1 and C2. RS, a serial resistor, maybe required for AT strip cut crystal or low frequency mode. Figure 6-17 is PCB layout suggestion. When the system works in Crystal mode (16MHz), a 10K OSCO. is connected between OSCI and
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 61
EM78P142
8-Bit Microprocessor with OTP ROM
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type Frequency Mode
LXT (100K~1 MHz) Ceramic Resonators MXT (1M~6 MHz) LXT2 (32.768kHz) LXT1 (100K~1 MHz)
Frequency
100kHz 200kHz 455kHz 1MHz 1.0 MHz 2.0 MHz 4.0 MHz 32.768kHz 100kHz 200kHz 455kHz 1MHz 455kHz 1.0 MHz 2.0 MHz 4.0 MHz 6.0 MHz 6.0 MHz 8.0 MHz 10.0 MHz 12.0 MHz 16.0 MHz
C1(pF)
67pF 30pF 30pF 30pF 30pF 30pF 30pF 40pF 67pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 15pF
C2(pF)
67pF 30pF 30pF 30pF 30pF 30pF 30pF 40pF 67pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 30pF 15pF
Crystal Oscillator
HXT2 (1~6 MHz)
HXT1 (6~16 MHz)
Circuit diagrams for serial and parallel modes Crystal/Resonator:
330 C OSCI 7404 7404 7404 330
Crystal
Figure 6-15 Serial Mode Crystal/Resonator Circuit Diagram
62 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
7404
4.7K
10K Vdd
O S CI
7404
10K
C rystal
10K
C1
C2
Figure 6-16 Parallel Mode Crystal/Resonator Circuit Diagram
Figure 6-17 Parallel Mode Crystal/Resonator Circuit Diagram
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 63
EM78P142
8-Bit Microprocessor with OTP ROM
6.10.3 External RC Oscillator Mode
For some applications that do not require precise timing calculation, the RC oscillator (Figure 6-18) could offer an effective cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation.
Figure 6-18 External RC Oscillator Mode Circuit
Vcc Rext
OSCI Cext
In order to maintain a stable system frequency, the values of the Cext should be no less than 20 pF, and the value of Rext should not be greater than 1 M. If the frequency cannot be kept within this range, the frequency can be affected easily by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator will become unstable because the NMOS cannot correctly discharge the capacitance current. Based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the way the PCB is layout, have certain effect on the system frequency.
64 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
The RC Oscillator frequencies:
Cext Rext
3.3k 20 pF 5.1k 10k 100k 3.3k 100 pF 5.1k 10k 100k 3.3k 300 pF 5.1k 10k 100k
Average Fosc 5V, 25C
3.5 MHz 2.4 MHz 1.27 MHz 140kHz 1.21 MHz 805kHz 420kHz 45kHz 550kHz 364kHz 188kHz 20kHz
Average Fosc 3V, 25C
3.0 MHz 2.2 MHz 1.24 MHz 143kHz 1.18 MHz 790kHz 418kHz 46kHz 526kHz 350kHz 185kHz 20kHz
Note: : Measured based on DIP packages.
2 3
1
: The values are for design reference only. : The frequency drift is 30%
6.10.4 Internal RC Oscillator Mode
The EM78P142 offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (16MHz, 1MHz, and 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below describes the EM78P142 internal RC drift with voltage, temperature, and process variations. Internal RC Drift Rate (Ta=25C, VDD=5V 5%, VSS=0V)
Internal RC Frequency
4 MHz 16 MHz 1 MHz 455kHz
Drift Rate Temperature (-40C ~+85C)
5% 5% 5% 5%
Voltage (2.3V~3.9V~5.5V)
5% 5% 5% 5%
Process
4% 4% 4% 4%
Total
14% 14% 14% 14%
Note: Theoretical values are for reference only. Actual values may vary depending on the actual process.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 65
EM78P142
8-Bit Microprocessor with OTP ROM
6.11 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply stabilizes in steady state. The EM78P142 POR voltage range is 1.6V ~ 1.8V. Under customer application, when power is switched OFF, Vdd must drop below 1.6V and remains at OFF state for 10s before power can be switched ON again. Subsequently, the EM78P142 will reset and work normally. The extra external reset circuit will work well if Vdd rises fast enough (50ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems.
6.11.1 Programmable WDT Time-out Period
The Option word (WDTPS) is used to define the WDT time-out period (18ms or 4.5ms ). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic resonators, the lower the operation frequency is, the longer is the required set-up time.
6 5
6.11.2 External Power-on Reset Circuit
The circuit shown in the following figure implements an external RC to produce a reset pulse. The pulse width (time constant) should be kept long enough to allow the Vdd to reach the minimum operating voltage. This circuit is used when the power supply has a slow power rise time. Because
Figure 6-19 External Power-on Reset Circuit
VDD /RESET R
D
Rin
C
the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40K. This way, the voltage at Pin /RESET is held below 0.2V. The diode (D) functions as a short circuit at power-down. The "C" capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
5
VDD=5V, WDT time-out period = 16.5ms 30%. VDD=3V, WDT time-out period = 18ms 30%. VDD=5V, WDT time-out period = 4.2ms 30%. VDD=3V, WDT time-out period = 4.5ms 30%.
6
66 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.11.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Figure 6-20 and Figure 6-21 show how to create a protection circuit against residual voltage.
VDD 33K Q1 /RESET 100K 1N4684 10K
VDD
Figure 6-20 Residual Voltage Protection Circuit 1
VDD R1 Q1 /RESET R3 R2
VDD
Figure 6-21 Residual Voltage Protection Circuit 2
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 67
EM78P142
8-Bit Microprocessor with OTP ROM
6.12 Code Option
EM78P142 has two CODE option words and one Customer ID word that are not part of the normal program memory.
Word 0
Bit 12 ~ Bit 0
Word1
Bit 12 ~ Bit 0
Word 2
Bit12 ~ Bit 0
6.12.1 Code Option Register (Word 0)
Word 0 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - - - Bit 2 Bit 1 Bit 0
Mne LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 monic 1 0 High Low High Low High Low High Low 4 clocks 2 clocks Disable Enable High Low High Low High Low
Protect
Disable Enable
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits
LVR1, LVR0
11 10 01 00
VDD Reset Level
2.4V 3.5V 4.0V
VDD Release Level
2.6V 3.7V 4.2V
NA (Power-on Reset) (Default)
Bits 10~9 (TYPE1 ~ TYPE0): Type selection for EM78P142.
TYPE 1, TYPE 0
00 01 10 11 Not used EM78P142 - 10Pin Not used Not used
MCU Type
68 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Bit 8 (CLKS):
Instruction period option bit 0 = two oscillator periods 1 = four oscillator periods (default) Refer to Section 6.15 for Instruction Set
Bit 7 (ENWDTB):
Watchdog timer enable bit 0 = Enable 1 = Disable (default)
Bits 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits
Oscillator Modes
ERC (External RC oscillator mode); P70/OSCO acts as P70 ERC (External RC oscillator mode); P70/OSCO acts as OSCO IRC (Internal RC oscillator mode); P70/OSCO acts as P70 IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO LXT1 (Frequency range of XT, mode is 1MHz ~ 100kHz) HXT1 (Frequency range of XT mode is 16MHz ~ 6MHz) LXT2 (Frequency range of XT mode is 32kHz) HXT2 (Frequency range of XT mode is 6MHz ~ 1MHz) (default)
1 2 3 3 3 3 3 2 2 1 1
OSC2
0 0 0 0 1 1 1 1
OSC1
0 0 1 1 0 0 1 1
OSC0
0 1 0 1 0 1 0 1
In ERC mode, OSCI is used as oscillator pin. OSCO/P54 is defined by code option Word 0 Bit 6 ~ Bit 4. In IRC mode, P54 is normal I/O pin. OSCO/P54 is defined by code option Word 0 Bit 6 ~ Bit 4. In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot and should not be defined as normal I/O pins.
Bit 3: Not used, (reserved). This bit is set to "0" all the time. Bits 2 ~ 0 (Protect): Protect Bits
Protect Bits
0 1
Protect
Enable Disable (default)
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 69
EM78P142
8-Bit Microprocessor with OTP ROM
6.12.2 Code Option Register (Word 1)
Word 1 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mne monic 1 0
- - -
- - -
- - -
RCOUT System _clk Open_ drain
- - -
- - -
- - -
C3 High Low
C2 High Low
C1 High Low
C0 High Low
RCM1 RCM0 High Low High Low
Bit 12: Bits 11~10:
Not used, (reserved). This bit is set to "0" all the time. Not used, (reserved). These bits are set to "1" all the time.
Bit 9 (RCOUT): Instruction clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain 1 = OSCO output instruction clock (default) Bit 8 & Bit 7: These bits must set to "0" all the time Bit 6: Not used, (reserved). This bit is set to "1" all the time.
Bit 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode C3, C2, C1, and C0 must be set to "1" only (auto-calibration). Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits
RCM 1
1 1 0 0
RCM 0
1 0 1 0
Frequency (MHz)
4 (Default) 16 1 455kHz
70 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.12.3 Customer ID Register (Word 2)
Word 2 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mne monic 1 0
- - -
- - -
- - -
NRM MOD1
RESET ENB P71
- - -
WDTPS 18ms 4.5ms
ID5 High Low
ID4 High Low
ID3 High Low
ID2 High Low
ID1 High Low
ID0 High Low
MOD2 /RESET
Bits 12 ~ 11: Bit 10: Bit 9 (NRM):
Not used (reserved). These bits are set to "1" all the time. Not used, (reserved). This bit is set to "0" all the time. 0 = Noise reject Mode 2, For multi-time circuit use, such as key scan and LED output. 1 = Noise reject Mode 1. For General input or output use (Default)
Bit 8 (RESETENB): RESET/P71 pin select bit 0 = P71 set to /RESET pin 1 = P71 is general purpose input pin or open-drain for output Port (default) Bit 7: Bit 6 (WDTPS): Not used (reserved). This bit is set to "1" all the time. WDT Time-out Period Selection bit
WDT Time
1 0
Watchdog Timer*
18 ms (Default) 4.5 ms
*Theoretical values, for reference only Bits 5 ~ 0: Customer's ID code
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 71
EM78P142
8-Bit Microprocessor with OTP ROM
6.13 Low Voltage Detector/Low Voltage Reset
The low voltage reset (LVR) and the low voltage detector (LVD) are designed for unstable power situation, such as external power noise interference or in EMS test condition. When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level (VRESET) and remains at 10s, the system reset will occur and the system will keep on reset status. The system will remain at reset status until Vdd voltage rises above Vdd release level. Refer to Figure 6-26. If Vdd drops below low voltage detector level, /LVD (the Bit 7 of RE) is cleared to "0' to show low voltage signal when LVD is enabled. This signal can be used for low voltage detection.
6.13.1 Low Voltage Reset
LVR property is set at Bits 12, 11 of Code Option Word 0. The detailed operation mode is as follows:
Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
- Protect
Bit 0
LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits.
LVR1, LVR0
11 10 01 00
VDD Reset Level
2.4V 3.5V 4.0V
VDD Release Level
2.6V 3.7V 4.2V
NA (Power-on Reset)
6.13.2 Low Voltage Detector
LVD property is set at the register, detailed operation mode is as follows: 6.13.2.1 IOCD1 (LVD Control Register)
Bit
EM78P142 ICE341N
7
-
6
-
5
LVR1
4
LVR0
3
2
1
LVD1 LVD1
0
LVD0 LVD0
LVDIE LVDEN LVDIE LVDEN
TYPE1 TYPE0
NOTE
IOCD1< 3 > register is both readable and writable Individual interrupt is enabled by setting its associated control bit in the IOCD1< 4 > to "1." Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
72 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
Bit 3 (LVDIE): Low voltage Detector interrupt enable bit. 0 = Disable Low voltage Detector interrupt 1 = Enable Low voltage Detector interrupt When the detect-low-level-voltage state is used to enter an interrupt vector or enter next instruction, the LVDIE bit must be set to "Enable". Bit 2 (LVDEN): Low Voltage Detector Enable bit 0 = Low voltage detector disable 1 = Low voltage detector enable Bits 1~0 (LVD1:0): Low Voltage Detector level bits.
LVDEN
1 1 1 1 0
LVD1, LVD0
11 10 01 00 xx
LVD voltage Interrupt Level Vdd 2.2V Vdd > 2.2V Vdd 3.3V Vdd > 3.3V Vdd 4.0V Vdd > 4.0V Vdd 4.5V Vdd > 4.5V NA
/LVD 0 1 0 1 0 1 0 1 0
6.13.2.2 RE (Interrupt Status 2 & Wake-up Control Register)
Bit 7
/LVD
Bit 6
LVDIF
Bit 5
ADIF
Bit 4
"0"
Bit 3
ADWE
Bit 2
"0"
Bit 1
ICWE
Bit 0
LVDWE
NOTE
RE < 6, 5 > can be cleared by instruction but cannot be set. IOCE0 is the interrupt mask register. Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0 = Low voltage is detected. 1 = Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDIF): Low Voltage Detector interrupt flag LVDIF reset to "0" by software or hardware. Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit. 0 = Disable Low Voltage Detect wake-up. 1 = Enable Low Voltage Detect wake-up. When the Low Voltage Detect is used to enter an interrupt vector or to wake up the IC from sleep/idle with Low Voltage Detect running, the LVDWE bit must be set to "Enable".
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 73
EM78P142
8-Bit Microprocessor with OTP ROM
6.13.3 Programming Process
Follow these steps to obtain data from the LVD: 1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level. 2. Set the LVDWE bit, if the wake-up function is employed. 3. Set the LVDIE bit, if the interrupt function is employed. 4. Write "ENI" instruction, if the interrupt function is employed. 5. Set LVDEN bit to 1 6. Write "SLEP" instruction or Polling /LVD bit. 7. Clear the low voltage detector interrupt flag bit (LVDIF) when Low Voltage Detector interrupt occurred. The LVD module uses the internal circuit. When LVDEN (Bit 2 of IOCD1) is set to "1", the LVD module is enabled. When LVDWE (bit 0 of RE) is set to "1", the LVD module will continue to operate during sleep/idle mode. If Vdd drops slowly and crosses the detect point (VLVD), the LVDIF (Bit 6 of RE) will be set to "1", the /LVD (Bit 7 of RE) will be cleared to "0", and the system will wake up from Sleep/Idle mode. When a system reset occurs, the LVDIF will be cleared. When Vdd remains above VLVD, LVDIF is kept at "0" and /LVD is kept at "1". When Vdd drops below VLVD, LVDIF is set to "1" and /LVD is kept at "0". If ENI instruction is executed, LVDIF will be set to "1", and the next instruction will branch to interrupt Vector 021H. The LVDIF is cleared to "0" by software. Refer Figure 6-24 below.
LVDIF is cleared by software
Vdd
VLVD VRESET
LVDIF
Internal Reset
>LVR Voltage drop
18ms System occur reset
Vdd < Vreset not longer than 10us, the system still keeps on operating
Figure 6-22 LVD/LVR Waveform Situation
74 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
6.14 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator time periods), unless the program counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In addition, the instruction set has the following features: 1. Every bit of any register can be set, cleared, or tested directly. 2. The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O registers. The following symbols are used in the Instruction Set table:
Convention: R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0000 0001 0010 0011 0100 rrrr 0000 0001 0010
Hex
0000 0001 0002 0003 0004 000r 0010 0011 0012
Mnemonic
NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A
Operation
No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R
Status Affected
None C None T, P T, P 1 None None None None None None 1 None None Z Z Z, C, DC Z, C, DC Z Z Z Z
0 0000 0001 0011 0013 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 0100 rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 75
EM78P142
8-Bit Microprocessor with OTP ROM
Binary Instruction
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
Hex
02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E9k 1EAK 1EBK
Mnemonic
AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k BANK k LCALL k LJMP k
Operation
A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A k R4(6) PC+1[SP], kPC kPC
Status Affected
Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None None 2 None 3 None None None None None None Z Z Z None Z, C, DC None None None
0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0 0 0 0 0 0 0111 0111 0111 100b 101b 110b 111b 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 1001 000k 1 1110 1010 kkkk k kkkk kkkk kkkk 1 1110 1011 kkkk k kkkk kkkk kkkk
Note:
1 2 3
This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only. This instruction is not recommended for RF operation. This instruction cannot operate under RF.
76 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
7
Absolute Maximum Ratings
Items
Temperature under bias Storage temperature Input voltage Output voltage Working Voltage Working Frequency -40C -65C Vss-0.3V Vss-0.3V 2.3V DC
Rating
to to to to to to 85C 150C Vdd+0.5V Vdd+0.5V 5.5V 16MHz
8
DC Electrical Characteristics
Ta= 25C, VDD= 5.0V, VSS= 0V
Symbol
FXT ERC VIHRC IERC1 VILRC IERC2 IIL VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 VIHX1 VILX1 IOH1
Parameter
Crystal: VDD to 5V ERC: VDD to 5V Input High Threshold Voltage (Schmitt Trigger) Sink current Input Low Threshold Voltage (Schmitt Trigger) Sink current
Condition
Two cycle with two clocks R: 5.1K, C: 100 pF OSCI in RC mode VI from low to high, VI=5V OSCI in RC mode VI from high to low, VI=2V
Min.
32.768k 760 3.9 21 1.7 16 -1 0.7Vdd -0.3V 0.7Vdd -0.3V 0.7Vdd -0.3V 2.9 1.7 -
Typ.
4 950 4 22 1.8 17 0 - - - - - - 3.0 1.8 -10
Max.
16 1140 4.1 23 1.9 18 1 Vdd+0.3V 0.3Vdd Vdd+0.3V 0.3Vdd Vdd+0.3V 0.3Vdd 3.1 1.9 -
Unit
MHz kHz V mA V mA A V V V V V V V V mA
Input Leakage Current for VIN = VDD, VSS input pins Input High Voltage (Schmitt Trigger) Input Low Voltage (Schmitt Trigger ) Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage (Schmitt trigger) Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage (Schmitt Trigger) Clock Input High Voltage Clock Input Low Voltage Output High Voltage (Ports 5, 6, 7) Ports 5, 6, 7 Ports 5, 6, 7 /RESET /RESET TCC,INT TCC,INT OSCI in crystal mode OSCI in crystal mode VOH = 0.9VDD
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 77
EM78P142
8-Bit Microprocessor with OTP ROM
Symbol
IOL1 IPH IPL ISB1 ISB2
Parameter
Output Low Voltage (Ports 5, 6,7) Pull-high current Pull-low current Power down current Power down current Operating supply current at two clocks Operating supply current at two clocks Operating supply current at two clocks Operating supply current at two clocks
Condition
VOL = 0.1VDD Pull-high active, input pin at VSS Pull-low active, input pin at Vdd All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled /RESET= 'High', Fosc=32kHz (Crystal type, CLKS="0"), Output pin floating, WDT disabled /RESET= 'High', Fosc=32kHz (Crystal type,CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled
Min.
- -50 20 - -
Typ.
20 - - - -
Max.
- -90 60 2.0 10
Unit
mA A A A A
ICC1
-
15
20
A
ICC2
-
15
25
A
ICC3
-
1.5
1.7
mA
ICC4
-
2.8
3.0
mA
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25C. These data are for design reference only.
Internal RC Electrical Characteristics (Ta=25C, VDD=5 V, VSS=0V)
Internal RC
4 MHz 16 MHz 1 MHz 455kHz
Drift Rate Temperature
25C 25C 25C 25C
Voltage
5V 5V 5V 5V
Min.
3.84 MHz 15.36 MHz 0.96 MHz 436.8kHz
Typ.
4 MHz 16 MHz 1 MHz 455kHz
Max.
4.16 MHz 16.64 MHz 1.04 MHz 473.2kHz
Internal RC Electrical Characteristics (Ta=-40 ~85C, VDD=2.2~5.5 V, VSS=0V)
Internal RC Temperature
4 MHz 16 MHz 1 MHz 455kHz -40C ~85C -40C ~85C -40C ~85C -40C ~85C
Drift Rate Voltage
2.2V~5.5V 2.2V~5.5V 2.2V~5.5V 2.2V~5.5V
Min.
3.44 MHz 13.76 MHz 0.86 MHz 391.3kHz
Typ.
4 MHz 16 MHz 1 MHz 455kHz
Max.
4.56 MHz 18.24 MHz 1.14 MHz 518.7kHz
78 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
8.1 AD Converter Characteristic
Vdd=2.5V to 5.5V, Vss=0V, Ta=-40 to 85C
Symbol
VAREF VASS VAI IAI1 IAI2 Ivdd Ivref Ivdd IVref
Parameter
Analog reference voltage Analog input voltage Analog supply current Analog supply current
Condition
VAREF - VASS 2.5V - VDD=VAREF=5.0V, VASS = 0.0V (V reference from Vdd) VDD=VAREF=5.0V, VASS = 0.0V (V reference from VREF) VDD=5.0V, OP used Output voltage swing from 0.2V to 4.8V ADREF=0, Internal VDD VDD=5.0V, VSS = 0.0V ADREF=1, External VREF VDD=VREF=5.0V, VSS = 0.0V VDD = 2.5 to 5.5V Ta=25C VDD= 2.5 to 5.5V Ta=25C VDD = 2.5 to 5.5V Ta=25C VDD=VAREF=5.0V, VASS = 0.0V VDD=VREF=5.0V, VSS = 0.0V VDD=VAREF=5.0V, VASS = 0.0V - VDD=VAREF=5.0V, VASS = 0.0V VDD=VAREF=5.0V, VASS = 0.0V VDD=VAREF=5.0V, VASS = 0.0V VDD=VAREF=5.0V, VASS =0.0V, RL=10K VDD=VAREF=5.0V, VASS = 0.0V VDD=5.0V0.5V
Min.
2.5 Vss VASS 750 -10 500 200 450 - - 0 0 0 0 0 0 0 4 15 0 0 4.7 0.1 0
Typ.
- - - 850 0 600 250 550
Max.
Vdd Vss VAREF 1000 +10 820 300 650 -10 12 8 4 0.9 8 4 4 10 - 15 VAREF 0.3 5 - 2
Unit
V V V A A A A A
IOP
OP current
RN1 RN2 LN1 LN2 DNL FSE1 FSE2 OE ZAI TAD TCN ADIV ADOV ADSR PSR
Resolution Resolution Linearity error Linearity error Differential nonlinear error Full scale error Full scale error Offset error Recommended impedance of analog voltage source ADC clock duration AD conversion time ADC OP input voltage range ADC OP output voltage swing ADC OP slew rate Power Supply Rejection
9 11 4 2 0.5 4 2 2 8 - - - 0.2 4.8 0.3 -
Bits Bits LSB LSB LSB LSB LSB LSB K s TAD V V V/s LSB
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. There is no current consumption when ADC is off other than minor leakage current. 3. AD conversion result will not decrease when an increase of input voltage and no missing code will result. 4. These parameters are subject to change without further notice.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 79
EM78P142
8-Bit Microprocessor with OTP ROM
8.2 Device Characteristics
The graphs below were derived based on a limited number of samples and they are provided for reference only. Hence, the device characteristic shown herein cannot be guaranteed as fully accurate. In these graphs, the data may be out of the specified operating warranted range.
IRC OSC Frequency (VDD=3V)
Frequency (MHz) .
Temperature oC
Figure 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
IRC OSC Frequency (VDD=5V)
Frequency (M Hz) .
Temperature ( )
Figure 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V
80 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
9
AC Electrical Characteristic
Ta=-40 to 85C, VDD=5V5%, VSS=0V
Symbol
Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Tdrc
Parameter
Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input time period Device reset hold time /RESET pulse width Watchdog timer duration Input pin setup time Input pin hold time Output pin delay time ERC delay time
Conditions
- Crystal type RC type - Ta = 25C Ta = 25C Ta = 25C - - Cload = 20 pF Ta = 25C
Min
45 100 500 (Tins+20)/N* 11.3 2000 11.3 - 15 45 1
Type
50 - - - 16.2 - 16.2 0 20 50 3
Max
55 DC DC - 21.6 - 21.6 - 25 55 5
Unit
% ns ns ns ms ns ms ns ns ns ns
Note:1. *N = selected prescaler ratio
2. Twdt1: The Option Word 1 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as set-up time (18ms). 3. Twdt2: The Option Word 1 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as set-up time (4.5ms). 4. These parameters are hypothetical (not tested) and are provided for design reference only. 5. Data under Minimum, Typical, and Maximum (Min, Typ, and Max) columns are based on hypothetical results at 25C. These data are for design reference use only. 6. The Watchdog timer duration is determined by code option Word1 (WDTPS).
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 81
EM78P142
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V 0.75VDD 0.25VDD GND+0.5V
TEST POINTS
0.75VDD 0.25VDD
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
82 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
APPENDIX A Package Type
OTP MCU
EM78P142SS10J/S
Package Type
SSOP
Pin Count
10
Package Size
150 mil
Green products do not contain hazardous substances. The third edition of Sony SS-00259 standard. Pb contents should be less the 100ppm Pb contents comply with Sony specs.
Part No.
Electroplate type Ingredient (%) Melting point (C) Electrical resistivity (-cm) Hardness (hv) Elongation (%)
EM78P142xJ/xS
Pure Tin Sn: 100% 232C 11.4 8~10 >50%
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 83
EM78P142
8-Bit Microprocessor with OTP ROM
B Packaging Configuration
B.1 EM78P142SS10
Symbal A A1 A2 D E E1 b b1 c c1 L e Min Normal Max
TITLE: SSOP 10L (150MIL)PACKAGE OUTLINE DIMENSION File : Edtion: A SSOP 10 L Unit : mm Scale: Free Material: Sheet:1 of 1
Figure B-1 EM78P142 10-pin SSOP Package Type
84 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
C Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Solder temperature=245 5C, for 5 seconds up to the stopper using a rosin-type flux Step 1: TCT, 65C (15mins)~150C (15mins), 10 cycles Step 2: Bake at 125C, TD (durance)=24 hrs Step 3: Soak at 30C /60% , TD (durance)=192 hrs
Remarks
-
Pre-condition
Step 4: IR flow 3 cycles (Pkg thickness 2.5mm or 3 Pkg volume 350mm ----225 5C) (Pkg thickness 2.5mm or 3 Pkg volume 350mm ----240 5C )
For SMD IC (such as SOP, QFP, SOJ, etc)
Temperature cycle test Pressure cooker test High temperature / High humidity test High-temperature storage life High-temperature operating life Latch-up ESD (HBM)
-65 (15mins)~150C (15mins), 200 cycles TA =121C, RH=100%, pressure=2 atm, TD (durance) = 96 hrs TA=85C , RH=85% , TD (durance)=168 , 500 hrs TA=150C, TD (durance)=500, 1000 hrs TA=125C, VCC=Max. operating voltage, TD (durance) =168, 500, 1000 hrs TA=25C, VCC=Max. operating voltage, 150mA/20V TA=25C, | 3KV |
- - - - - - IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, IP_PS,OP_PS,IO_PS, VDD-VSS(+),VDD_VSS (-)mode
ESD (MM)
TA=25C, | 300V |
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise-caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program.
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 85
EM78P142
8-Bit Microprocessor with OTP ROM
D How to Use the ICE 341N
ICE 341 for EM78P142
W1
W1
OSCI P55
P55/OSCI Pin Select
I/O Port (P55)
OSCI P55
Crystal, ERC (OSCI)
Oscillator IRC Modes select I/O Port (P55) Oscillator Crystal, ERC Modes select Crystal (OSCI)
86 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
JP3
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 87
EM78P142
8-Bit Microprocessor with OTP ROM
DIP IDC PLUG
1
20
10
11
DIP IDC PLUG
88 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
EM78P142
8-Bit Microprocessor with OTP ROM
E
Comparison between V-Package and U-Package Version
This microcontroller device is comprised of the older V-package version and the newer U-package version. In the newer U-package version, a Code Option NRM is added and various features such as Crystal mode Operating frequency range and IRC mode wake-up time from sleep mode to normal mode, have been modified to favorably meet users' requirements. The following table is provided for quick comparison between the two package version and for user convenience in the choice of the most suitable product for their application.
Item
Level Voltage Reset Crystal mode Operating frequency range at 0C~ 70C IRC mode wake-up time ( Sleep Normal ) Condition: 5V, 4 MHz Code Option x Added a Code Option NRM 80s 10s
EM78P142-V
4.0V, 3.5V, 2.7V DC ~ 12 MHz, 4.5V DC ~ 8 MHz, 3.0V DC ~ 4 MHz, 2.1V
EM78P142-U
4.0V, 3.5V, 2.4V DC ~ 16 MHz, 4.5V DC ~ 8 MHz, 3.0V DC ~ 4 MHz, 2.1V
EM78P142-V Package
EM78P142-U Package
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)
* 89
EM78P142
8-Bit Microprocessor with OTP ROM
90 *
Product Specification (V1.0) 01.25.2008
(This specification is subject to change without further notice)

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